Data Sheet

LJ1269HC
Rev1.0 Page 68 Web: www.ljelect.com
RegIrqFlags2
(0x28)
7
FifoFull
r
0
Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
6
FifoNotEmpty
r
0
Set when FIFO contains at least one byte, else cleared
5
FifoLevel
r
0
Set when the number of bytes in the FIFO strictly
exceeds FifoThreshold, else cleared.
4
FifoOverrun
rwc
0
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
transmission / reception.
3
PacketSent
r
0
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx.
2
PayloadReady
r
0
Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared, is Ok). Cleared when FIFO is empty.
1
CrcOk
r
0
Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
0
-
r
0
unused
RegRssiThresh
(0x29)
7-0
RssiThreshold
rw
0xE4
*
RSSI trigger level for Rssi interrupt :
- RssiThreshold / 2 [dBm]
RegRxTimeout1
(0x2A)
7-0
TimeoutRxStart
rw
0x00
Timeout interrupt is generated TimeoutRxStart*16*Tbit
after switching to Rx mode if Rssi interrupt doesn‟t occur
(i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is
disabled
RegRxTimeout2
(0x2B)
7-0
TimeoutRssiThresh
rw
0x00
Timeout interrupt is generated
TimeoutRssiThresh*16*Tbit after Rssi interrupt if
PayloadReady interrupt doesn‟t occur.
0x00: TimeoutRssiThresh is disabled
Sub GHz FSK/OOK Transceiver Module DATASHEET