Data Sheet

LJ1269HC
Rev1.0 Page 63 Web: www.ljelect.com
RegListen1 (0x0D)
7-6
ListenResolIdle
rw
10
Resolution of Listen mode Idle time (calibrated RC osc):
00 → reserved
01 → 64 us
10 → 4.1 ms
11 → 262 ms
5-4
ListenResolRx
rw
01
Resolution of Listen mode Rx time (calibrated RC osc):
00 → reserved
01 → 64 us
10 → 4.1 ms
11 → 262 ms
3
ListenCriteria
rw
0
Criteria for packet acceptance in Listen mode:
0 → signal strength is above RssiThreshold
1 → signal strength is above RssiThreshold and
SyncAddress matched
2-1
ListenEnd
rw
01
Action taken after acceptance of a packet in Listen mode:
00 → chip stays in Rx mode. Listen mode stops and must be
disabled (see section 4.3).
01 → chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. It then goes to the mode defined by
Mode. Listen mode stops and must be disabled (see section 4.3).
10 → chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. Listen mode then resumes in
Idle state. FIFO content is lost at next Rx wakeup.
11 → Reserved
0
-
r
0
unused
RegListen2 (0x0E)
7-0
ListenCoefIdle
rw
0xf5
Duration of the Idle phase in Listen mode.
t ListenIdle = ListenCoefIdle ∗ ListenResolIdle
RegListen3 (0x0F)
7-0
ListenCoefRx
rw
0x20
Duration of the Rx phase in Listen mode (startup time
included, see section 4.2.3)
t ListenRx = ListenCoefRx ∗ ListenResolRx
Version code of the chip. Bits 7-4 give the full revisio number; bits
3-0 give the metal mask revision number.
RegVersion
(0x10)
7-0
Version
r
0x24
Sub GHz FSK/OOK Transceiver Module DATASHEET