Data Sheet

LJ1269HC
Rev1.0 Page 53 Web: www.ljelect.com
If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is
the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues otherwise it's
stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the CRC was successful.
An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available
in the FIFO can also be read in Sleep/Standby mode.
If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting
CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails.
5.5.5. AES
AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can
work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its
value in Sleep mode.
As shown in Figure 33 and Figure 34 above the message part of the Packet can be encrypted and decrypted with the cipher
128- cipher key stored in the configuration registers.
Tx Processing
User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit command.
On Tx command the Packet handler state machine takes over the control and If encryption is enabled then the message inside
the FIFO is read in blocks of 16 bytes (padded with 0s if needed), encrypted and stored back to FIFO. All this processing is done
in Tx mode before enabling the packet handling state machine. Only the Message part of the packet is encrypted and preamble,
sync word, length byte, address byte and CRC are not encrypted.
Once the encryption is done the Packet handling state machine is enabled to transmit the data.
Rx Processing
The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because these parameters were
not encrypted.
Once the complete packet has been received. The data is read from the FIFO, decrypted and written back to FIFO. The
PayloadReady interrupt is issued once the decrypted data is ready in the FIFO for reading via the SPI interface.
The AES encryption/decryption cannot be used on the fly i.e. while transmitting and receiving data. Thus when AES
encryption/decryption is enabled, the FIFO acts as a simple buffer. This buffer is filled before initiating any transmission. The
data in the buffer is then encrypted before the transmission can begin. On the receive side the decryption is initiated only once
the complete packet has been received in the buffer.
The encryption/decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64 bytes)
it can take up to 28 us for completing the cryptographic operations.
The receive side sees the AES decryption time as a sequential delay before the PayloadReady interrupt is available.
The Tx side sees the AES encryption time as a sequential delay in the startup of the Tx chain, thus the startup time of the Tx will
increase according to the length of data.
Sub GHz FSK/OOK Transceiver Module DATASHEET