LJelect Sub GHz FSK/OOK Transceiver Module : Data Sheet : Page 48

LJ1269HC

Rev1.0 Page 48 Web: www.ljelect.com

5.4.2. Tx Processing

In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the data is

illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state anytime

outside the grayed out setup/hold zone.

Figure 29. Tx Processing in Continuous Mode

Note the use of DCLK is required when the modulation shaping is enabled (see section 3.3.5).

5.4.3. Rx Processing

If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is

provided.

Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on

DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated

below.

Figure 30. Rx Processing in Continuous Mode

Note in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK

signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode).