Data Sheet

LJ1269HC
Rev1.0 Page 44 Web: www.ljelect.com
 FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that
when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty is updated to
low state the currently started read operation must be completed. In other words, FifoNotEmpty state must be checked
after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read; FifoNotEmpty = 0: no
more byte to read).
 FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
 FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (inRx
mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also
be cleared.
 PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.
 FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.
Figure 26. FifoLevel IRQ Source Behavior
Note - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be
dynamically updated by only changing the FifoThreshold parameter
- FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation
FIFO Clearing
Table below summarizes the status of the FIFO when switching between different modes
Sub GHz FSK/OOK Transceiver Module DATASHEET