LJelect Sub GHz FSK/OOK Transceiver Module : Data Sheet : Page 43

LJ1269HC

Rev1.0 Page 43 Web: www.ljelect.com

The first byte is the address byte. It is made of:

 wnr bit, which is 1 for write access and 0 for read access

 7 bits of address, MSB first

The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO

in case of read access. The data byte is transmitted MSB first.

Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and

re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO

address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte

received.

The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a

special case of FIFO / BURST mode with only 1 data byte transferred.

During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register

before the write operation.

5.2.2. FIFO

Overview and Shift Register (SR)

In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO (First In

First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.

The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift

register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs them

serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data from the

demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.

Figure 25. FIFO and Shift Register (SR)

Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from all

modes except from Tx)

Size

The FIFO size is fixed to 66 bytes.

Interrupt Sources and Flags