Data Sheet

LJ1269HC
Rev1.0 Page 4 Web: www.ljelect.com
5.5.5. AES ................................................................................................................................................................................................ 53
5.5.6. Handling Large Packets ............................................................................................................................................................... 54
5.5.7. Packet Filtering ............................................................................................................................................................................. 54
5.5.8. DC-Free Data Mechanisms .......................................................................................................................................................... 56
6. Configuration and Status Registers .......................................................................................................................................................... 58
6.1. General Description ............................................................................................................................................................................. 58
6.2. Common Configuration Registers ...................................................................................................................................................... 61
6.3. Transmitter Registers .......................................................................................................................................................................... 64
6.4. Receiver Registers ................................................................................................................................................................................ 65
6.5. IRQ and Pin Mapping Registers ........................................................................................................................................................ 67
6.6. Packet Engine Registers ...................................................................................................................................................................... 69
6.7. Temperature Sensor Registers ............................................................................................................................................................ 72
6.8. Test Registers ....................................................................................................................................................................................... 72
7. Application Information ............................................................................................................................................................................ 73
7.1. Crystal Resonator Specification ......................................................................................................................................................... 73
7.2. Reset of the Module ............................................................................................................................................................................. 73
7.2.1. POR ............................................................................................................................................................................................... 73
7.2.2. Manual Reset ................................................................................................................................................................................ 74
7.3. Reference Design .................................................................................................................................................................................. 75
8. Packaging Information .............................................................................................................................................................................. 77
8.1. Package Outline Drawing ................................................................................................................................................................... 77
8.2. Tray packaging .................................................................................................................................................................................... 78
9. Recommended PCB Land Pattern ............................................................................................................................................................ 79
10. Ordering Information .............................................................................................................................................................................. 80
11. Revision History ........................................................................................................................................................................................ 80
12. Contact us: ............................................................................................................................................................................................. 81
Index of Figures Page
Figure 1. Block Diagram .................................................................................................................................................................................. 8
Figure 2. Marking Diagram ............................................................................................................................................................................. 9
Figure 3. TCXO Connection .......................................................................................................................................................................... 15
Figure 4. Transmitter Block Diagram ........................................................................................................................................................... 18
Figure 5. Output Power Curves .................................................................................................................................................................... 21
Figure 6. Receiver Block Diagram ................................................................................................................................................................ 22
Figure 7. AGC Thresholds Settings ............................................................................................................................................................... 23
Figure 8. RSSI Dynamic Curve .................................................................................................................................................................. 27
Figure 9. Cordic Extraction ........................................................................................................................................................................... 28
Figure 10. OOK Peak Demodulator Description ......................................................................................................................................... 28
Figure 11. Floor Threshold Optimization ..................................................................................................................................................... 29
Figure 12. Bit Synchronizer Description ...................................................................................................................................................... 30
Figure 13. FEI Process ................................................................................................................................................................................... 31
Sub GHz FSK/OOK Transceiver Module DATASHEET