Data Sheet

LJ1269HC
Rev1.0 Page 36 Web: www.ljelect.com
Figure 17. Rx Startup - No AGC, no AFC
Figure 18. Rx Startup - AGC, no AFC
Figure 19. Rx Startup - AGC and AFC
The different timings shown above are as follows:
 Group delay of the analog front end: Tana = 20 us
 Channel filter‟s group delay in FSK mode: Tcf = 21 / (4.RxBw)
 Channel filter‟s group delay in OOK mode: Tcf = 34 / (4.RxBw)
 DC Cutoff‟s group delay: Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw)
 PLL lock time after AFC adjustment: Tpllafc = 5 / PLLBW (PLLBW = 300 kHz)
 AFC sample time: Tafc = 4 x Tbit (also denoted TS_AFC in the general
specification)
 RSSI sample time: Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw) (aka TS_RSSI)
Note The above timings represent maximum settling times, and shorter settling times may be observed in real cases
Sub GHz FSK/OOK Transceiver Module DATASHEET