Data Sheet

LJ1269HC
Rev1.0 Page 17 Web: www.ljelect.com
3.2.4. Lock Time
PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. W hen
using the built-in sequencer, the LJ1269HC optimizes the startup time and automatically starts the receiver or the transmitter
when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the
specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range.
When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:
In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the
expected lock times.
3.2.5. Lock Detect Indicator
A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its locking
range. Please refer to Table 21 and Table 22 to map this interrupt to the desired pins.
Note The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated with
large frequency deviation settings.
Sub GHz FSK/OOK Transceiver Module DATASHEET
T
PLLAFC
=
5
𝑃𝐿𝐿𝐵𝑊