LJelect Sub GHz FSK/OOK Transceiver Module : Data Sheet : Page 16

LJ1269HC

Rev1.0 Page 16 Web: www.ljelect.com

3.2.2. CLKOUT Output

The reference frequency, or a fraction of it, can be provided on DIO5 by modifying bits ClkOut in RegDioMapping2. Two typical

applications of the CLKOUT output include:

To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made

available in any operation mode except Sleep mode and is automatically enabled at power on reset. ‹ To provide an oscillator

reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance.

Note to minimize the current consumption of the LJ1269HC, please ensure that the CLKOUT signal is disabled when

not required.

3.2.3. PLL Architecture

The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a fractional-N sigma- delta

PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the

loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit.

VCO

The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO leakage

in receiver mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO during

transmission.

The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is performed

each time the LJ1269HC PLL is activated. Automatic calibration times are fully transparent to the end-user, as their processing

time is included in the TS_TE and TS_RE specifications.

PLL Bandwidth

The bandwidth of the LJ1269HC Fractional-N PLL is wide enough to allow for:

High speed FSK modulation, up to 300 kb/s, inside the PLL bandwidth ‹ Very fast PLL lock times, enabling both short startup

and fast hop times required for frequency agile applications

Carrier Frequency and Resolution

The LJ1269HC PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency

range, and is given by:

The carrier frequency is programmed through RegFrf, split across addresses 0x07 to 0x09:

F

R F

= F

STEP

× Frf(23,0)

Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least

significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as m- ary FSK,

where frequency modulation is achieved by changing the programmed RF frequency.