Data Sheet

LJ1269HC
Rev1.0 Page 15 Web: www.ljelect.com
3. ModuleDescription
This section describes in depth the architecture of the LJ1269HC low-power, highly integrated transceiver.
3.1 Power Supply Strategy
The LJ1269HC employs an advanced power supply scheme, which provides stable operating characteristics over the full
temperature and voltage range of operation. This includes the full output power of +20dBm maintained from 2.4 to 3.6V. The
LJ1269HC can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be
connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation of the
built-in voltage regulators.
3.2 Frequency Synthesis
The LO generation on the LJ1269HC is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with automatic
calibration.
3.2.1. Reference Oscillator
The crystal oscillator is the main timing reference of the LJ1269HC . It is used as a reference for the frequency synthesizer and
as a clock for the digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. W hen using the built- in
sequencer, the LJ1269HC optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To
manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will only be
made available on the output buffer when a stable XO oscillation is achieved.
An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at address
0x59 should be set to 1, and the external clock has to be provided on XTA. XTB should be left open. The peak- peak amplitude
of the input signal must never exceed 2.4 V. Please consult your TCXO supplier for an appropriate value of decoupling
capacitor, CD.
Figure 3. TCXO Connection
Sub GHz FSK/OOK Transceiver Module DATASHEET