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HDK Manual

Table of Contents

littleBits HDK Manual .................................................................................................... 1

1.0.0 Documentation Conventions .................................................................................... 1

2.0.0 Required Engineering Deliverables ......................................................................... 2

2.1.0 Delivery of Items to littleBits ................................................................................... 3

2.2.0 Examples ................................................................................................................... 3

3.0.0 Design Requirements ............................................................................................... 3

4.0.0 Preparations .............................................................................................................. 6

5.0.0 Product Design Requirement (PRD) ....................................................................... 7

6.0.0 Schematic (SCH) ...................................................................................................... 8

7.0.0 Printed Circuit Board (PCB) .................................................................................. 11

7.1.0 Component Choice and Placement ...................................................................... 13

7.2.0 Routing ..................................................................................................................... 15

7.3.0 Silkscreen ................................................................................................................ 16

7.4.0 Design Rule Check ................................................................................................ 17

8.0.0 Bill of Materials (BOM) .......................................................................................... 17

9.0.0 Firmware .................................................................................................................. 18

1.0.0 Documentation Conventions

1.0.1 Standard text. This is the standard typeface.

1.0.2

Italics represent information that may change depending on the

design.

1.0.3 The pound sign # represents indeterminate numerals.

Summary of content (20 pages)

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HDK Manual Table of Contents littleBits HDK Manual .................................................................................................... 1 1.0.0 Documentation Conventions .................................................................................... 1 2.0.0 Required Engineering Deliverables ......................................................................... 2 2.1.0 Delivery of Items to littleBits .................................................................................
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1.0.4 “ALL CAPS” in quotations are references to specific elements of software tools like EagleCAD. The littleBits company will be represented by the abbreviation “LB”. 2.0.0 Required Engineering Deliverables 2.0.1 Product Requirements Document (PRD) conforming to LB standards as described in this document. Template PRDs are provided by LB (HDK-hardware-dev-manual/Design/Templates for PRD). 2.0.2 Schematic Diagram (SCH) conforming to LB standards as described in this document.
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2.1.0 Delivery of Items to littleBits 2.1.1 If your bitLab submission is approved, a GitHub repository will be created for your module and initialized with LB preferred folder structure. 2.1.2 Replace the templates and placeholders in the repository with your deliverables, and commit and push your changes to GitHub. 2.2.0 Examples 2.2.
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Pin 2: SIG (signal, 0 to 5 V continuous) Pin 3: GND (ground, 0VDC) Figure 1: Male and female bitSnap™ connector pinouts 3.0.4 All inputs must be high impedance. The preferred input impedance must be equal to or greater than 1 M (megOhm). It is acceptable to have a lower impedance if the circuit design does not permit 1 M. In these cases, the input impedance may be no lower than 100 K.
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3.0.5 All outputs must be low impedance, with symmetric drive characteristics (yields same performance when either sinking or sourcing current.) The output impedance must be less than 100 ohms. This is typically achieved by using a buffer or follower circuit at the output. Outputs must never be allowed to float. Outputs must be rail-to-rail. Figure 3: Example of an output stage, included in the Eagle templates 3.0.6 Polarity conventions must be observed unless otherwise specified.
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3.0.9 Inputs: Every bitSnap input must have a series 10K current limiting resistor on the SIG line (see Figure 2). 3.0.10 Inputs: Every bitSnap input must have a shunt TVS diode, or equivalent ESD countermeasures (see Figure 2). 3.0.11 Inputs: Floating bitSnap inputs are not permitted. For this reason, every input needs to have a pull-down, pull-up, or reference network. To maintain high input impedance, this network must usually be greater or equal to 1 M.
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boards 5.0.0 Product Design Requirement (PRD) 5.0.1 The PRD should be created by the developer from the template provided by LB. The template is available in Design/Templates for PRD/prd_template.xls. A copy of the template will be provided by LB in the module repo if the project is accepted. 5.0.2 The PRD should contain the following sections: OVERVIEW: PRODUCT TYPE: May be either WIRE, POWER, INPUT or OUTPUT. DESCRIPTION OF PRODUCT: A concise but complete description of the functionality of the bit.
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Standard and Custom Size References in Design/Eagle Templates for SCH and BRD. ELECT. REQUIREMENTS: All requirements should remain as set in the template unless there is a specific reason to change or add to them. Consult with LB with any questions. DESIGN REQUIREMENTS: All requirements should remain as set in the template unless there is a specific reason to change or add to them. The requirement “Output bitSnap passes input signal through” only applies for OUTPUT bits.
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moduleType##-moduleName-v03(#_#x).sch | | | | | | | (#_#x) = | | | first digit: schematic revision number | | | second digit: PCB revision number | | | the “x” connotes that the design is in progress and | | | has not been released for manufacturing. | | v03 = the littleBits system is version 0.3 | moduleName = the name of the module moduleType## = module type is one of the following: p (power), i (input), o (output), or w (wire), followed by a one or 2-digit number.
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does not exist it must be created and verified by littleBits. 6.0.8 The circuit should read from left to right when possible. 6.0.9 Male bitSnap connectors are inputs, and must be placed on the left side of the frame. Female bitSnap connectors are outputs, and must be located on the right side of the frame. 6.0.10 The bitSnap symbol terminals are labeled VCC, SIG, and GND. Each of these pins must be connected to the NET corresponding to those labels. 6.0.
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6.0.16 GND symbols should face downward and VCC symbols should face upward whenever possible. 6.0.17 Functions of interface elements (switches etc.) should be labeled on the info layer. 6.0.18 Nets that are not directly connecting two points should be labeled. SIG net should always be flagged with a cross-reference label. 7.0.0 Printed Circuit Board (PCB) 7.0.1 The PCB layout must be designed in EagleCAD version 6 or later. 7.0.2 File name must be in this format: moduleType##-moduleName-v03(#_#x).
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7.0.4 Set the PCB layout primary grid to 0.1mm. Set the alternate grid to 0.01mm. 7.0.5 The origin of the FRAME-LETTER package must be set to coordinates (0, 0). All the other parts of the design must be placed within the bounds of this frame. 7.0.6 The board outline and the dimension layer must not be altered. 7.0.7 All packages used must be from the LITTLEBITS140915.lbr littleBits Eagle library. If specific device does not exist it must be created and verified by littleBits. 7.0.
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7.1.0 Component Choice and Placement 7.1.1 bitSnap connectors must not be moved from their original positions in the templates. 7.1.2 All components besides bitSnap connectors which are included in the templates may be moved and their traces rerouted if necessary. 7.1.3 Resistors, capacitors, inductors, and other 2-lead passives should be SMD0603 chip devices unless design requirements do not allow it. 7.1.
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performance in mind but with attention paid to maintaining balance and symmetry between the X and Y-axis of the PCB. See reference layouts in Appendix A. 7.1.8 Placing components over bottom layer silkscreen is acceptable. Neat component placement takes priority. See figures 1 and 2, and refer to section 7.3.0 for more information on the silkscreen layers. Figure 4: Example of neat component placement. Note how components are placed in line with each other. 7.1.
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components. Smash parts as needed. Names should generally be placed along the long side of the component (lengthwise) and the value along the short side (widthwise). This can be reversed if the length of the text is inversely proportional and the values are longer than the names. 7.2.0 Routing 7.2.1 The traces which are already routed in the templates may be altered if necessary. 7.2.2 Minimum track width is 0.008 inches (0.2032mm). Default track width is 0.016 inches (0.4064mm). 7.2.
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Polygon Pour = Solid Isolate = 0 (the isolate dimension is set in the Design Rules) Thermals On Orphans Off 7.2.7 The PCB revision number (the second number in parentheses in the file name from section 6.0.2 above) must be placed on the bottom copper layer in bottom right corner (screen view). Font specifications are: Size = 0.8128mm Ratio = 12% Font = vector This text is already placed in the PCB templates. Change the X in “revX” to the PCB revision number. 7.3.0 Silkscreen 7.3.
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7.3.4 The module number and name must be placed on the tPlace layer. They should be centered on the X-axis and the highest point of the text should be 0.7mm from the right edge of the PCB. The number and name should be spelled out using any vector font. 7.4.0 Design Rule Check 7.4.1 Board layouts must be verified using the littleBits DRC file provided. 7.4.2 The DRC file must be run with only layers 1 to 20 turned on. 7.4.3 Width error of revision number copper text can be ignored. 8.0.
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Rev: for bitSnaps Rev is v0.3, for PCB Rev is the PCB rev#, for all others rev is na. Qty Per: Quantity of item per bit. MFG: Manufacturer name Mfr Part Number: Manufacturer Part Number Ref Loc: reference location or locations of the part in the PCB and schematic. SUB ALLOWED?: Generally YES for resistors and capacitors, NO for all other items. 8.0.3 BOM Revisions take the form of the date of the revision in the form YYMMDD, for example 150403 for April 3rd, 2015. 8.0.
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9.0.2 In general, module firmware should be developed using a toolchain provided or recognized by the manufacturer of the microcontroller. For example, we like the Atmel Studio IDE and avr-gcc for Atmel processors. 9.0.3 Code should be human-readable and commented well. All global variables should have comments detailing their purpose and use.
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be the exact same hex that is burned onto the physical prototype that is sent to LB.