User's Manual

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Power UP Sequence
PDn must remain asserted for a minimum of 1 ms after VDD33 is stable
For auto reference clock detection, the sleep clock (32.768 KHz) must be used and must
be stable before PDn is de-asserted
RESETn should be inactive value (asserted high)
Power Down Sequence

PDn must be turned off simultaneously with or before VDD33
SDIO INTERFACE
SDIO Protocol Timing Diagram—Normal Mode