User's Manual

COMPANY CONFIDENTIAL
26
AUDIO
AV2DATA0
O
I2S or left justified audio data output. Typically connected to external D/A converter input
or to external DSP for further audio processing. Used for main left and right channel audio
output data. See Note 3.
AV2CTRL0
O
LRCK, audio data word clock at the audio sample rate (Fs). Maximum currently supported
frequency is 192kHz.
AV2CTRL1
O
MCLK, audio master clock at 256Fs. This can be used to clock an external D/A converter
or DSP.
AV2CLK
O
SCLK, audio data bit clock at 64Fs. Allows for up to 32 audio data bits per sample word.
AV4DATA1
O
SPDIF format output. Can support samples rates up to 192kHz, so the maximum
instantaneous frequency on this pin is 24.576MHz.
AV4DATA0
I
SPDIF input. Not used at present. Leave open.
AV2DATA1
O
I2S or left justified audio data output. Not used at present. Leave open.
AOUTLP/AOUTLN,
AOUTRP/AOUTRN
O
Differential stereo output from PWM-DAC, right and left channels. These signals require
analog low pass filtering. SMSC is not recommending using the PWM-DAC outputs
because of the potential for high out-of-band noise and uncharacterized audio quality.
SMSC recommends using an external D/A converter connected to AV2DATA0.
AV2DATA2
I
I2S or left justified audio data input. Can be driven from an optional external A/D converter
used to interface to iPod analog output or other analog audio sources. If not used, leave
open.
AV2DATA3
I
I2S or left justified audio data input. Not used at present. Leave open.
CONTROL
NCS3
I
This signal is configured as GPIO-17 and is currently not used. DM870A-internal pull-up.
Leave this pin open.
PDOUT0
I
Factory Reset. GPIO-04. Return the CnE to factory settings. High-active input,
DM870A-internal pull-down. Pull to GND with a 10kohm resistor, unless return to factory
settings from a hardware control is needed. Normally, return to factory settings is controlled
from the host controller via SPI register. This pin is only monitored during the boot up
process.
VCO0
I
Infrared sensor input. GPIO-05. This is a Schmitt-Trigger input and can handle inputs with
slow slopes. Used for aDMP firmware builds for infrared remote control sensor output
connection to DM870A. For applications with a host controller, pull this pin to +3.3V via a
10kohm resistor.
AV3CLK
O
ETH_NRESET Low-active reset for the on-board ethernet PHY. This output is driven by the
DM870A. GPIO-12. Leave this pin open.
AV3CTRL0, AV3CTRL1
I/O
I2C_SCL, I2C_SDA bus created by GPIO-13 and GPIO-14.
No internal pull-ups; Use 4.7kohm pull up resistor on each pin to +3.3V. Maximum
frequency is 400kHz.
NRESET_MOD
I
Low-active input to reset the module. This signal must be driven by an external reset
generator, or by a GPIO output from a host controller. See the application section of this
data sheet for the timing requirements for NRESET_MOD. Includes internal 10K pull-up
resistor to +3.3V.
NPD_RF
I
Active low input to shut down the power for the 802.11 RF section. Internal 10kohm
pull-up resistor to +3.3V. Leave open if powering down the RF section is not required.