User's Manual
Table Of Contents
- Description
- Features
- Ordering Information
- Absolute Maximum Ratings
- Electrical Specifications
- Typical Performance Graphs
- Pin Assignments
- Pin Descriptions
- Module Pin Assignments
- Module Dimensions
- Theory of Operation
- Module Description
- Overview
- Addressing Modes
- Automatic Addressing
- Address Register Use
- Acknowledgements and Assured Delivery
- Frequency Hopping Spread Spectrum
- Compatibility with the 250 Series
- Networking
- Transmitting Packets
- Receiving Packets
- Using the Buffer Empty (BE) Line
- Exception Engine
- Carrier Sense Multiple Access (CSMA)
- Using the Command Response (CRESP) Line
- Using the CMD Line
- AES Encryption
- Using the MODE_IND Line
- Using the PB Line
- Restore Factory Defaults
- Using the Low Power Features
- Baud Rate and Transmitter Output Power
- The Command Data Interface
- Reading from Registers
- Writing to Registers
- Command Length Optimization
- Example Code for Encoding Read/Write Commands
- The Command Data Interface Command Set
- Typical Applications
- Usage Guidelines for FCC Compliance
- Additional Testing Requirements
- Information to the user
- Product Labeling
- FCC RF Exposure Statement
- Antenna Selection
- Power Supply Requirements
- Antenna Considerations
- Interference Considerations
- Pad Layout
- Castellation Version Reference Design
- Microstrip Details
- Board Layout Guidelines
- Helpful Application Notes from Linx
- Production Guidelines
- Hand Assembly
- Automated Assembly
- General Antenna Rules
- Common Antenna Styles
- Regulatory Considerations
- Notes
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80 81
NVCYCLE - Non-Volatile Refresh Cycles
Non-Volatile Address = 0xC4-0xC5
These read-only non-volatile registers contain the number of lifetime
refresh cycles performed for the non-volatile memory. The minimum lifetime
refreshes is 2,000 refresh cycles. Beyond this the refreshes may not be
complete and the module’s operation can become unpredictable.
Between 8 and 150 non-volatile write operations can be made before
a refresh cycle is necessary. Writing the registers from lowest to highest
address maximizes the number of write operations per refresh cycle.
It is recommended to write the desired default values to non-volatile
memory and use the volatile registers for values that change frequently.
These registers show the total number of refresh cycles that have occurred.
This gives an indication of the remaining life expectancy of the memory.
Figure 86 shows the Non-Volatile Refresh Cycles registers.
HumPRO-A
TM
Series Non-Volatile Refresh Cycles Registers
Name
Non-Volatile
Address
Description
NVCYCLE1 0xC4 MSB of the number of refresh cycles
NVCYCLE0 0xC5 LSB of the number of refresh cycles
Figure 86: HumPRO-A
TM
Series Non-Volatile Refresh Cycles Registers
LSTATUS - Output Line Status
Volatile Address = 0xC6
This register contains the logic states of the output indicator lines, providing
information to the host processor while using fewer GPIO lines.
Each bit in the byte that is returned by the read represents the logic state
of one of the output indicator lines. Figure 88 shows which line each bit
represents.
Figure 87: HumPRO-A
TM
Series Transceiver Output Line Status Command and Response
HumPRO-A
TM
Series Output Line Status
Read Command Read Response
Header Size Escape Escape Address ACK Address Value
0xFF 0x03 0xFE 0xFE 0x46 0x06 0xC6 LSTATUS
HumPRO-A
TM
Series Output Line Status LSTATUS Values
LSTATUS Bit Line Status
0 EX – Exception, 1 = exception has occurred
1 PA_EN – PA Enable, 1 = the transmitter is active
2 LNA_EN – LNA Enable, 1 = the receiver is active
3 CTS – Clear To Send, 1 = incoming data buffer near full
4 MODE_IND – Mode Indicator, 1 = RF data transfer is active (TX or RX)
5 BE – Buffer Empty, 1 = UART buffer is empty
6 Reserved
7 Reserved
Figure 88: HumPRO-A
TM
Series Output Line Status LSTATUS Values