User's Guide

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Restore Factory Defaults
The transceiver is reset to factory default by taking the PB line high briefly
4 times, then holding PB high for more than 3 seconds. Each brief interval
must be high 0.1 to 2 seconds and low 0.1 to 2 seconds. (1 second
nominal high / low cycle). The sequence helps prevent accidental resets.
Once the sequence is recognized, the MODE_IND line blinks in groups
of three until the PB line goes low. After PB goes low, the non-volatile
configurations are set to the factory default values and the module is
restarted. The default UART data rate is 9,600bps.
If the timing on PB does not match the specified limits, the sequence is
ignored. Another attempt can be made after lowering PB for at least 3
seconds.
Using the Low Power Features
The module supports several low-power features to save current in
battery-powered applications. This allows the module to be asleep most of
the time, but be able to quickly wake up, send data and go back to sleep.
Taking the Power Down (POWER_DOWN) line low places the module into
the lowest power state. In this mode, the internal voltage regulator and all
oscillators are turned off. All circuits powered from the voltage regulator
are also off. The module is not functional while in this mode and current
consumption drops to below 6µA. Taking the line high wakes the module.
When the POWER_DOWN line is high, the IDLE register determines sleep
operation.
If IDLE is set to 1 during normal operation, the module sends an ACK byte,
waits for completion of an active transmission, then goes into sleep mode.
Unsent data in the incoming UART data buffer does not inhibit sleep.
During sleep mode, the output lines are in the states in Figure 34.
A rising transition on the POWER_DOWN or CMD_DATA_IN lines wakes
the module. If a negative-going pulse is needed to generate a rising edge,
the pulse width should be greater than 1 µs.
Other lines also wake the module but it immediately goes back to sleep.
Floating inputs should be avoided since they may cause unintended
transitions and cause the module to draw additional current.
If the volatile registers have been corrupted during sleep, a software reset
is performed. This restarts the module as if power were cycled. This can be
caused by power surges or brownout among other things.
After the module wakes up, it sets the IDLE register to 0 (active). If the
WAKEACK register is set to 1, then the module outputs the 0x06 byte on
the CMD_DATA_OUT line. The CRESP line is taken high and the module
then begins normal operation.
Pulsing RESET low causes the module to restart rather than continue from
sleep.
Output Line Sleep States
Output Line Sleep State
EX Unchanged
CRESP Low
LNA_EN Low
PA_EN Low
TXD High
CTS High
MODE_IND Low
BE Unchanged
Figure 34: HumPRO
TM
Series Output Line Sleep States