Datasheet

LTC6990
19
6990fc
For more information www.linear.com/LTC6990
Figure 14. Digitally Controlled Oscillator with V
SET
Variation Eliminated
6990 F14
LTC6990
OE
GND
SET
OUT
V
+
DIV
C1
0.1µF
R1
R2
R
SET
V
+
R
VCO
–
+
V
+
1/2
LTC6078
LTC1659
V
+
V
CC
REF
GND
V
OUT
µP
D
IN
CLK
CS/LD
f
OUT
=
1MHz • 50kΩ
N
DIV
•R
VCO
• 1+
R
VCO
R
SET
−
D
IN
4096






D
IN
= 0 to 4095
Additionally, by choosing the VCO’s specifications
shrewdly, the frequency error (in percent) due to V
SET
variation is reduced to ∆V
SET
/V
SET
= ±3%. To realize this
improvement, the design must abide by three conditions.
First, the V
IN
voltage must be positive throughout the
range. Second, choose V
MAX
/V
MIN
≥ f
MAX
/f
MIN
. Last,
choose R
VCO
/R
SET
≥ R4/R3.
Figure 13 shows a design similar to the previous design
example where the V
MIN
voltage is now specified to be
0.4V. This satisfies the V
MAX
/V
MIN
≥ f
MAX
/f
MIN
condition
and the design assures that the output frequency error
due to V
SET
variation is only ±3%.
Eliminating V
SET
Error Effects with DAC Frequency
Control
Many DACs allow for the use of an external reference.
If such a DAC is used to provide the V
CTRL
voltage, the
V
SET
error is eliminated by buffering V
SET
and using it as
the DAC’s reference voltage, as shown in Figure 14. The
DAC’s output voltage now tracks any V
SET
variation and
eliminates it as an error source. The SET pin cannot be
tied directly to the reference input of the DAC because
the current drawn by the DAC’s REF input would
affect
the frequency.
APPLICATIONS INFORMATION
I
SET
Extremes (Master Oscillator Frequency Extremes)
Pushing I
SET
outside of the recommended 1.25µA to 20µA
range forces the master oscillator to operate outside of the
62.5kHz to 1MHz range in which it is most accurate. The
oscillator will still function with reduced accuracy in its
extended range (see the Electrical Characteristics section).
The LTC6990 is designed to function normally for I
SET
as low as 1.25µA. At approximately 500nA, the oscillator
output will be frozen in its current state. For N
DIV
= 1 or 2,
OUT will halt in a low state. But for larger divider ratios,
it
could halt in a high or low state. This avoids introduc-
ing short
pulses while modulating a very low frequency
output.
Note that the output will not be
disabled as when
OE is low (e.g. the output will not enter a high impedance
state if Hi-Z = 1).
At the other extreme, the master oscillator frequency can
reach 2MHz for I
SET
= 40μA (R
SET
= 25k). It is not recom-
mended to operate the master oscillator beyond 2MHz
because the accuracy of the DIV pin ADC will suffer.