Datasheet

LTM9012
5
9012f
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 6)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
ADC Supply Voltage (Note 10)
l
1.7 1.8 1.9 V
OV
DD
ADC Output Supply Voltage (Note 10)
l
1.7 1.8 1.9 V
V
CC
Amplifier Supply Voltage (Note 10)
l
2.7 3.3 3.6 V
I
VDD
ADC Supply Current Sine Wave Input
l
298 320 mA
I
OVDD
ADC Output Supply Current 2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
27
49
31
54
mA
mA
I
VCC
Amplifier Supply Current
l
208 224 mA
P
DISS
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
1271
1311
1473
1517
mW
mW
P
SLEEP
3 mW
P
NAP
85 mW
P
DIFFCLK
Power Decrease with Single-Ended
Encode Mode Enabled
20 mW
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 6)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
S
Sampling Frequency (Note 10, Note 11)
l
5 125 MHz
t
ENCL
ENC Low Time (Note 9) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
100
100
ns
ns
t
ENCH
ENC High Time (Note 9) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
100
100
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
0 ns
Digital Data Outputs (R
TERM
= 100Ω Differential, C
L
= 2pF to GND on Each Output)
t
SER
Serial Data Bit Period 2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8• f
S
)
1/(7•f
S
)
1/(6•f
S
)
1/(16•f
S
)
1/(14•f
S
)
1/(12•f
S
)
sec
sec
sec
sec
sec
sec
t
FRAME
FR to DCO Delay (Note 9)
l
0.35• t
SER
0.5• t
SER
0.65• t
SER
sec
t
DATA
DATA to DCO Delay (Note 9)
l
0.35• t
SER
0.5• t
SER
0.65• t
SER
sec
t
PD
Propagation Delay (Note 9)
l
0.7n + 2• t
SER
1.1n + 2• t
SER
1.5n + 2• t
SER
sec
t
R
Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns
t
F
Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns
DCO Cycle-Cycle Jitter t
SER
= 1ns 60 ps
P-P
Pipeline Latency 6 Cycles
SPI Port Timing (Note 9)
t
SCK
SCK Period Write Mode
Read Back Mode, C
SDO
= 20pF, R
PULLUP
= 2k
l
l
40
250
ns
ns
t
S
CS to SCK Setup Time
l
5 ns
t
H
SCK to CS Setup Time
l
5 ns
t
DS
SDI Setup Time
l
5 ns
t
DH
SDI Hold Time
l
5 ns
t
DO
SCK Falling to SDO Valid Read Back Mode, C
SDO
= 20pF, R
PULLUP
= 2k
l
125 ns