Datasheet

LTM9012
21
9012f
applicaTions inForMaTion
GROUNDING AND BYPASSING
The LTM9012 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane in the first layer beneath the ADC is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
Bypass capacitors are integrated inside the package; ad-
ditional capacitance is optional.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
LAYOUT RECOMMENDATIONS
The pin assignments of the LTM9012 allow a flow-through
layout that makes it possible to use multiple parts in a
small area when a large number of ADC channels are
required. The LTM9012 has similar layout rules to other
BGA packages. The layout can be implemented with 6mil
blind vias and 5mil traces. The pinout has been designed
to minimize the space required to route the analog and
digital traces. The analog and digital traces can essentially
be routed within the width of the package. This allows
multiple packages to be located close together for high
channel count applications. Trace lengths for the analog
inputs and digital outputs should be matched as well as
possible. Table 5 lists the trace lengths for the analog inputs
and digital outputs inside the package from the die pad to
the package pad. These should be added to the PCB trace
lengths for best matching.
Figures 7 through Figure 11 show an example of a good
PCB layout.
HEAT TRANSFER
Most of the heat generated by the LTM9012 is transferred
from the die through the bottom side of the package
through numerous ground pins onto the printed circuit
board. For good electrical and thermal performance, these
pins should be connected to the internal ground planes
by an array of vias.
Table 5. Internal Trace Lengths
PIN NAME (mm)
Q9 01A
–
0.535
Q10 01A
+
0.350
R11 01B
–
2.185
R12 01B
+
2.216
R9 02A
–
0.174
R10 02A
+
0.667
S11 02B
–
2.976
S12 02B
+
2.972
S2 03A
–
3.033
S3 03A
+
3.031
R4 03B
–
0.752
R5 03B
+
0.370
R2 04A
–
2.130
R3 04A
+
2.125
Q4 04B
–
0.332
Q5 04B
+
0.527
A12 CH1
–
7.741
A11 CH1
+
7.723
A9 CH2
–
4.632
A8 CH2
+
4.629
A6 CH3
–
3.987
A5 CH3
+
3.988
A3 CH4
–
7.892
A2 CH4
+
7.896
P1 CLK
–
3.317
N1 CLK
+
3.325
P4 CS 0.241
S9 DCO
–
1.912
S10 DCO
+
1.927
S4 FR
–
2.097
S5 FR
+
2.082
P10 PAR/SER 0.226
P5 SCK 1.553
P9 SD0 0.957
P3 SDI 1.184