Datasheet

LTM9012
16
9012f
Table 1. Maximum Sampling Frequency for All Serialization Modes. The Sampling Frequency for Potential Slower Speed Grades
Cannot Exceed f
SAMPLE(MAX)
.
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, f
S
(MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE
2-Lane 16-Bit Serialization 125 4 • f
S
f
S
8 • f
S
2-Lane 14-Bit Serialization 125 3.5 • f
S
0.5 • f
S
7 • f
S
2-Lane 12-Bit Serialization 125 3 • f
S
f
S
6 • f
S
1-Lane 16-Bit Serialization 62.5 8 • f
S
f
S
16 • f
S
1-Lane 14-Bit Serialization 71.4 7 • f
S
f
S
14 • f
S
1-Lane 12-Bit Serialization 83.3 6 • f
S
f
S
12 • f
S
applicaTions inForMaTion
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25μs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTM9012 are serialized LVDS
signals. Each channel outputs two bits at a time (2-lane
mode). At lower sampling rates there is a one bit per chan-
nel option (1-lane mode). The data can be serialized with
16-, 14-, or 12-bit serialization (see the Timing Diagrams
for details). Note that with 12-bit serialization the two LSBs
are not available—this mode is included for compatibility
with potential 12-bit versions of these parts.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is 1Gbps,
so the maximum sample rate of the ADC will depend on
the serialization mode as well as the speed grade of the
ADC (see Table 1). The minimum sample rate for all seri-
alization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
DD
which is isolated from
the A/D core power.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by control register A2 in the serial pro-
gramming mode. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the
parallel programming mode the SCK pin can select either
3.5mA or 1.75mA.