Datasheet

LTM9012
15
9012f
applicaTions inForMaTion
Figure 5. Sinusoidal Encode Drive Figure 6. PECL or LVDS Encode Drive
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should be
treated as analog signals—do not route them next to digital
traces on the circuit board. There are two modes of opera-
tion for the encode inputs: the differential encode mode
(Figure 3), and the single-ended encode mode (Figure 4).
The differential encode mode is recommended for sinusoi-
dal, PECL, or LVDS encode inputs (Figure 5 and Figure 6).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
Figure 3. Equivalent Encode Input Circuit
for Differential Encode Mode
Figure 4. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
V
DD
LTM9012
9012 F03
ENC
–
ENC
+
15k
V
DD
DIFFERENTIAL
COMPARATOR
30k
30k
ENC
+
ENC
–
9012 F04
0V
1.8V TO 3.3V
LTM9012
CMOS LOGIC
BUFFER
50Ω
100Ω
0.1µF
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTM9012
9012 F05
ENC
–
ENC
+
ENC
+
ENC
–
PECL OR
LVDS
CLOCK
0.1µF
0.1µF
9012 F06
LTM9012
above V
DD
(up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC
–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC
+
should have fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
–
is connected
to ground and ENC
+
is driven with a square wave encode
input. ENC
+
can be taken above V
DD
(up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC
+
threshold
is 0.9V. For good jitter performance ENC
+
should have fast
rise and fall times.