Datasheet

LTM9012
13
9012f
block DiagraM
9012 BD
LTM9012
14-BIT
ADC CORE
CH 1
ANALOG
INPUT
SHDN1
CH 4
ANALOG
INPUT
CH 3
ANALOG
INPUT
CH 2
ANALOG
INPUT
14-BIT
ADC CORE
V
DD/2
OUT1A
+
OUT1A
–
OUT1B
+
OUT1B
–
OUT2A
+
OUT2A
–
OUT2B
+
OUT2B
–
OUT3A
+
OUT3A
–
OUT3B
+
OUT3B
–
OUT4A
+
OUT4A
–
OUT4B
+
OUT4B
–
SDO
SDI
SCK
CS
PAR/SER
DCO
±
FR
±
DATA
SERIALIZER
MODE
CONTROL
REGISTERS
PLL
ENC
+
ENC
–
V
REF
1.25V
REFERENCE
RANGE
SELECT
14-BIT
ADC CORE
14-BIT
ADC CORE
1.8V
OV
DD
1.8V
V
DD
3.3V
V
CC
DIFF. REF.
AMP.
REF
BUFFER
SENSE GND
REFH REFL
SHDN2
SHDN3
V
DD/2
SHDN4
Figure 1. Block Diagram