Datasheet

LTM9012
11
9012f
pin FuncTions
V
CC1
(H10, H13): Channel 1 Amplifier Supply. V
CC
is
internally bypassed to ground with 0.1µF in parallel with
0.01µF ceramic capacitors, additional bypass capacitance
is optional. The recommended operating voltage is 3.3V.
V
CC2
(C8, C12): Channel 2 Amplifier Supply. V
CC
is in-
ternally bypassed to ground with 0.1µF in parallel with
0.01µF ceramic capacitors, additional bypass capacitance
is optional. The recommended operating voltage is 3.3V.
V
CC3
(C2, C6): Channel 3 Amplifier Supply. V
CC
is in-
ternally bypassed to ground with 0.1µF in parallel with
0.01µF ceramic capacitors, additional bypass capacitance
is optional. The recommended operating voltage is 3.3V.
V
CC4
(H1, H4): Channel 4 Amplifier Supply. V
CC
is in-
ternally bypassed to ground with 0.1µF in parallel with
0.01µF ceramic capacitors, additional bypass capacitance
is optional. The recommended operating voltage is 3.3V.
V
DD
(N4, N5, N9, N10): ADC Analog Supply. V
DD
is inter-
nally bypassed to ground with 0.1µF ceramic capacitors,
additional bypass capacitance is optional. The recom-
mended operating voltage is 1.8V.
OV
DD
(R7, R8, S8): ADC Digital Output Supply. OV
DD
is internally bypassed to ground with 0.1µF ceramic ca-
pacitors, additional bypass capacitance is optional. The
recommended operating voltage is 1.8V.
GND: Ground. Use multiple vias close to pins.
CH1
+
(A11): Channel 1 Noninverting Analog Input.
CH1
–
(A12): Channel 1 Inverting Analog Input.
CH2
+
(A8): Channel 2 Noninverting Analog Input.
CH2
–
(A9): Channel 2 Inverting Analog Input.
CH3
+
(A5): Channel 3 Noninverting Analog Input.
CH3
–
(A6): Channel 3 Inverting Analog Input.
CH4
+
(A2): Channel 4 Noninverting Analog Input.
CH4
–
(A3): Channel 4 Inverting Analog Input.
SHDN1 (G11): Channel 1 Amplifier Shutdown. Connect-
ing SHDN1 to V
CC
or floating results in normal (active)
operating mode. Connecting SHDN1 to GND results in a
low power shutdown state on amplifier 1.
SHDN2 (D9): Channel 2 Amplifier Shutdown. Connect-
ing SHDN2 to V
CC
or floating results in normal (active)
operating mode. Connecting SHDN2 to GND results in a
low power shutdown state on amplifier 2.
SHDN3 (D3): Channel 3 Amplifier Shutdown. Connect-
ing SHDN3 to V
CC
or floating results in normal (active)
operating mode. Connecting SHDN3 to GND results in a
low power shutdown state on amplifier 3.
SHDN4 (G1): Channel 4 Amplifier Shutdown. Connect-
ing SHDN4 to V
CC
or floating results in normal (active)
operating mode. Connecting SHDN4 to GND results in a
low power shutdown state on amplifier 4.
ENC
+
(N1): Encode Input. Conversion starts on the rising
edge.
ENC
–
(P1): Encode Complement Input. Conversion starts
on the falling edge.
CS (P4): In serial programming mode, (PAR/SER = 0V),
CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
control registers. In the parallel programming mode (PAR/
SER = V
DD
), CS selects 2-lane or 1-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (P5): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
DD
), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (P3): In serial programming mode, (PAR/SER = 0V),
SDI is the serial interface data Input. Data on SDI is clocked
into the mode control registers on the rising edge of SCK.
In the parallel programming mode (PAR/SER = V
DD
), SDI
can be used to power down the part. SDI can be driven
with 1.8V to 3.3V logic.
SDO (P9): In serial programming mode, (PAR/SER = 0V),
SDO is the optional serial interface data output. Data on
SDO is read back from the mode control registers and can
be latched on the falling edge of SCK. SDO is an open-
drain NMOS output that requires an external 2k pull-up
resistor to 1.8V – 3.3V. If read back from the mode control
registers is not needed, the pull-up resistor is not neces-
sary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = V
DD
), SDO is an input
that enables internal 100Ω termination resistors. When
used as an input, SDO can be driven with 1.8V to 3.3V
logic through a 1k series resistor.