Datasheet

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LTM9012

9012f

Typical applicaTion

FeaTures DescripTion

Quad 14-Bit, 125Msps ADC

with Integrated Drivers

The LTM

9012 is a 4-channel, simultaneous sampling

14-bit µModule

analog-to-digital converter (ADC) with

integrated, fixed gain, differential ADC drivers. The low

noise amplifiers are suitable for single-ended drive and

pulse train signals such as imaging applications. Each

channel includes a lowpass filter between the driver out-

put and ADC input.

DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 1.2LSB

RMS

The digital outputs are serial LVDS and each channel out-

puts two bits at a time (2-lane mode). At lower sampling

rates there is a one bit option (1-lane mode). The LVDS

drivers have optional internal termination and adjustable

output levels to ensure clean signal integrity.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An internal clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

Single-Ended Sensor Digitization

applicaTions

4-Channel Simultaneous Sampling ADC with

Integrated, Fixed Gain, Differential Drivers

68.3dB SNR

78dB SFDR

Low Power: 1.27W Total, 318mW per Channel

1.8V ADC Core and 3.3V Analog Input Supply

Serial LVDS Outputs: 1 or 2 Bits per Channel

Shutdown and Nap Modes

11.25mm × 15mm BGA Package

Industrial Imaging

Medical Imaging

Multichannel Data Acquisition

Nondestructive Testing

L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of

Linear Technology Corporation. All other trademarks are the property of their respective owners.

LTM9012, 125Msps, 70MHz FFT

9012 TA01a

LTM9012

FPGA

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

IMAGE

SENSOR

PIPELINE

ADC

INTERNAL

REFERENCE & SUPPLY

BYPASS CAPACITORS

PLL

SCK ENC

ENC

–

SDI SDO PAR/SERCS

ENCODE CLOCK

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

–

DCO

–

DATA

SERIALIZER

ENCODER

AND

LVDS

DRIVERS

1.8V

3.3V

•

REF

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–90

–80

–10

25155 45

9012 TA01b

–100

–110

–120

–30

–20

–40

–50

–60

–70

302010 50

Summary of content (28 pages)

PAGE 1
LTM9012 Quad 14-Bit, 125Msps ADC with Integrated Drivers Description Features n n n n n n n n 4-Channel Simultaneous Sampling ADC with Integrated, Fixed Gain, Differential Drivers 68.3dB SNR 78dB SFDR Low Power: 1.27W Total, 318mW per Channel 1.8V ADC Core and 3.3V Analog Input Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Shutdown and Nap Modes 11.
PAGE 2
LTM9012 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltages VDD, OVDD................................................. –0.3V to 2V VCC........................................................ –0.3V to 5.5V Analog Input Voltage (CHn +, CHn –, SHDNn ) (Note 3)........................................................–0.3V to VCC Analog Input Voltage (PAR/SER, SENSE) (Note 4)......................................... –0.3V to (VDD + 0.
PAGE 3
LTM9012 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l 14 TYP MAX UNITS Bits Integral Linearity Error Differential Analog Input (Note 7) l –5 ±1.2 5 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.3 0.
PAGE 4
LTM9012 Internal Reference Characteristics full operating temperature range, otherwise specifications are at TA = 25°C. The l denotes the specifications which apply over the PARAMETER CONDITIONS MIN TYP MAX VREF Output Voltage IOUT = 0 1.225 1.250 1.275 VREF Output Temperature Drift UNITS V ±25 VREF Output Resistance –400μA < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V ppm/°C 7 Ω 0.
PAGE 5
LTM9012 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 6) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VDD ADC Supply Voltage (Note 10) l 1.7 1.8 1.9 UNITS V OVDD ADC Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V VCC Amplifier Supply Voltage (Note 10) l 2.7 3.3 3.
PAGE 6
LTM9012 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: Input pins are protected by steering diodes to either supply. If the inputs should exceed either supply voltage, the input current should be limited to less than 10mA.
PAGE 7
LTM9012 Timing Diagrams 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N tENCH ENC– N+1 tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tDATA tSER tPD tSER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 9012 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 2-Lane Output
PAGE 8
LTM9012 Timing Diagrams 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D1 D0 0 tSER 0 SAMPLE N-6 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 SAMPLE N-5 0 D13 D12 D11 D10 SAMPLE N-4 9012 TD04 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D
PAGE 9
LTM9012 Timing Diagrams 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D5 D4 D3 tSER D2 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 SAMPLE N-5 SAMPLE N-4 9012 TD06 OUT#B+, OUT#B– ARE DISABLED SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D
PAGE 10
LTM9012 Typical Performance Characteristics IOVDD vs Sample Rate, 5MHz Sine Wave Input –1dBFS 60 0 50 64K Point FFT, fIN = 5MHz, –1dBFS, SENSE = VDD 0 –10 –10 –20 –20 –30 IOVDD (mA) 30 20 1-LANE 1.75mA 1-LANE 3.5mA 2-LANE 1.75mA 2-LANE 3.5mA 10 0 0 25 50 75 100 SAMPLE RATE (Msps) 125 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 40 –40 –50 –60 –70 –80 –90 –110 –110 –120 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) 0 –10 –20 –20 0.5 0.4 0.
PAGE 11
LTM9012 Pin Functions VCC1 (H10, H13): Channel 1 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VCC2 (C8, C12): Channel 2 Amplifier Supply. VCC is internally bypassed to ground with 0.1µF in parallel with 0.01µF ceramic capacitors, additional bypass capacitance is optional. The recommended operating voltage is 3.3V. VCC3 (C2, C6): Channel 3 Amplifier Supply.
PAGE 12
LTM9012 Pin Functions PAR/SER (P10): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal.
PAGE 13
LTM9012 Block Diagram 3.3V 1.8V VCC LTM9012 1.8V VDD OVDD OUT1A+ CH 1 ANALOG INPUT OUT1A– 14-BIT ADC CORE SHDN1 OUT1B+ OUT1B– DATA SERIALIZER VDD/2 OUT2A+ CH 2 ANALOG INPUT OUT2A– 14-BIT ADC CORE OUT2B+ OUT2B– SHDN2 OUT3A+ CH 3 ANALOG INPUT OUT3A– 14-BIT ADC CORE OUT3B+ OUT3B– SHDN3 VDD/2 OUT4A+ CH 4 ANALOG INPUT OUT4A– 14-BIT ADC CORE OUT4B+ OUT4B– SHDN4 ENC+ DCO± PLL ENC– VREF FR± 1.
PAGE 14
LTM9012 Applications Information Converter Operation The LTM9012 is a low power, 4-channel, 14-bit, 125Msps A/D converter that is powered by a 1.8V ADC supply and 3.3V driver supplies. Each input includes a fixed gain, differential amplifier. The analog inputs can be driven differentially or single-ended. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines.
PAGE 15
LTM9012 Applications Information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 3), and the single-ended encode mode (Figure 4). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 5 and Figure 6).
PAGE 16
LTM9012 Applications Information Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%.
PAGE 17
LTM9012 Applications Information Optional LVDS Driver Internal Termination Digital Output Randomizer In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver.
PAGE 18
LTM9012 Applications Information Sleep and Nap Modes Parallel Programming Mode The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 3mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL.
PAGE 19
LTM9012 Applications Information The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers.
PAGE 20
LTM9012 Applications Information REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 ILVDS2 ILVDS1 ILVDS0 Bits 7-5 D4 TERMON D3 OUTOFF D2 OUTMODE2 D1 OUTMODE1 D0 OUTMODE0 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current Bit 4 Bit 3 Bits 2-0 111 = 1.
PAGE 21
LTM9012 Applications Information Grounding and Bypassing Table 5. Internal Trace Lengths PIN NAME (mm) Q9 01A– 0.535 Q10 01A+ 0.350 R11 01B– 2.185 R12 01B+ 2.216 R9 02A– 0.174 R10 02A+ 0.667 S11 02B– 2.976 S12 02B+ 2.972 S2 03A– 3.033 S3 03A+ 3.031 R4 03B– 0.752 R5 03B+ 0.370 R2 04A– 2.130 R3 04A+ 2.125 Q4 04B– 0.
PAGE 22
LTM9012 Applications Information Figure 7.
PAGE 23
LTM9012 Applications Information Figure 8.
PAGE 24
LTM9012 Applications Information Figure 9.
PAGE 25
LTM9012 Applications Information Figure 10.
PAGE 26
J6 TP5 GND TP4 5V TO 6V TP2 GND TP1 V+ 3V TO 6V C28 OPT R69 0Ω R13 OPT R18 0Ω C11 1µF C2 1µF 3 1 3 1 J14 2 3 1 2 R64 1k VDD C31 0.01µF • • J8 CLK– C30 0.01µF C32 OPT R24 OPT T1 MABA-007159-000000 3 1 R63 1k VDD GND BYP OUT SEN/ADJ LT1763 J13 R14 OPT 2 R62 1k VDD SHDN IN GND BYP OUT SEN/ADJ LT1763-1.8 SHDN C21 0.01µF J12 2 R61 1k VDD R60 DNS J11 C10 4.7µF C1 4.
PAGE 27
0.50 ±0.025 Ø 221x PACKAGE TOP VIEW 0.80 1.60 2.40 SUGGESTED PCB LAYOUT TOP VIEW 0.00 4 0.80 PIN “A1” CORNER 3.75 4.25 4.00 E 1.60 aaa Z 4.80 4.00 3.20 2.40 3.20 4.80 Y Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6.40 5.
PAGE 28
LTM9012 Typical Application Single-Ended Drive with Unity Gain Example SENSE VDD OVDD VCC4 VCC3 VCC1 1.8V VCC2 3.3V LTM9012 464Ω 1% 0V TO 3V PULSE SIGNAL 464Ω 1% 3V OUTA– • • • • • • SHDN1 SDO SHDN2 FR– +IN + SHDN3 FR+ ¼ LTC6254 –IN – SHDN4 DCO– PAR/SER DCO+ GND ENC– ENC+ VREF CS 1k 1% SDI 0.1µF OUTA+ CH1– SCK 1.5V REFERENCE CH1+ 9012 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2170-14/LTC2171-14/ LTC2172-14 14-Bit, 25Msps/40Msps/65Msps 1.