Datasheet
LTM9008-14/
LTM9007-14/LTM9006-14
6
90067814f
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTM9008-14 LTM9007-14 LTM9006-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
I
VDD
Analog Supply Current Sine Wave Input
l
357 400 232 275 175 250 mA
I
OVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
32
60
50
94
58
104
32
58
48
92
54
102
30
56
48
90
54
100
mA
mA
mA
mA
P
DISS
Power Dissipation 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
700
751
733
812
824
907
475
522
504
583
592
679
369
416
401
477
547
630
mW
mW
mW
mW
P
SLEEP
Sleep Mode Power 2 2 2 mW
P
NAP
Nap Mode Power 170 170 170 mW
P
DIFFCLK
Power Decrease With Single-Ended Encode Mode Enabled
(No Decrease for Sleep Mode)
40 40 40 mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTM9008-14 LTM9007-14 LTM9006-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
S
Sampling Frequency (Notes 10,11)
l
5 65 5 40 5 25 MHz
t
ENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
7.69
7.69
100
100
11.88
2
12.5
12.5
100
100
19
2
20
20
100
100
ns
ns
t
ENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
7.69
7.69
100
100
11.88
2
12.5
12.5
100
100
19
2
20
20
100
100
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (R
TERM
= 100Ω Differential, C
L
= 2pF to GND on Each Output)
t
SER
Serial Data Bit Period 2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 • f
S
)
1/(7 • f
S
)
1/(6 • f
S
)
1/(16 • f
S
)
1/(14 • f
S
)
1/(12 • f
S
)
s
s
s
s
s
s
t
FRAME
FR to DCO Delay (Note 8)
l
0.35 • t
SER
0.5 • t
SER
0.65 • t
SER
s
t
DATA
DATA to DCO Delay (Note 8)
l
0.35 • t
SER
0.5 • t
SER
0.65 • t
SER
s
t
PD
Propagation Delay (Note 8)
l
0.7n + 2 • t
SER
1.1n + 2 • t
SER
1.5n + 2 • t
SER
s
t
R
Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns
t
F
Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns
DCO Cycle-Cycle Jitter t
SER
= 1ns 60 ps
P-P
Pipeline Latency 6 Cycles