Datasheet

LTM9008-14/
LTM9007-14/LTM9006-14
28
90067814f
APPLICATIONS INFORMATION
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode.
After the Reset SPI
Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only.
Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND)
D7 D6 D5 D4 D3 D2 D1 D0
DCSOFF RAND TWOSCOMP SLEEP NAP_8 NAP_5 NAP_4 NAP_1
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
Bit 6 RAND Data Output
Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = vData Output Randomizer Mode On
Bit 5 TWOSCOMP Tw o’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Tw o’s Complement Data Format
Bits 4-0 SLEEP: NAP_X Sleep/Nap Mode Control Bits
00000 = Normal Operation
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 4 in Nap Mode
0X1XX = Channel 5 in Nap Mode
01XXX = Channel 8 in
Nap Mode
1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serial interface that program the A/D mode control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W
bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address
bits (A6:A
0) will be read back on the SDO pin (see the
Timing Diagrams section). During a read back command
the register is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and
read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 4 shows a map of the mode control registers.