Datasheet

LTM4649
4
4649f
For more information www.linear.com/LTM4649
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at T
A
= 25°C (Note 2). V
IN
= 12V per typical application.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
GBP Gain Bandwidth Product 3 MHz
CMRR Common Mode Rejection (Note 6) 60 dB
I
DIFFOUT
DIFFOUT Current Sourcing 2 mA
R
IN
Input Resistance DIFFP, DIFFN to GND 80 kΩ
V
PGOOD
PGOOD Trip Level V
FB
With Respect to Set Output
V
FB
Ramping Negative
V
FB
Ramping Positive
–10
10
%
%
V
PGL
PGOOD Voltage Low I
PGOOD
= 2mA 0.1 0.3 V
INTV
CC
Linear Regulator
V
INTVCC
Internal V
CC
Voltage 4.8 5 5.2 V
V
INTVCC
Load Reg INTV
CC
Load Regulation I
CC
= 0mA to 50mA 0.9 %
Oscillator and Phase-Locked Loop
f
SYNC
SYNC Capture Range 250 800 kHz
f
S
Nominal Switching Frequency 400 450 500 kHz
R
MODE
Mode Input Resistance 250 kΩ
V
IH_CLKIN
Clock Input Level High 2.0 V
V
IL_CLKIN
Clock Input Level Low 0.8 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Notes are automatically numbered when you apply
the note style.
Note 2: The LTM4649 is tested under pulsed load conditions such that T
J
≈
T
A
. The LTM4649E is guaranteed to meet performance specifications over
the 0°C to 125°C internal operating temperature range. Specifications over
the –40°C to 125°C internal operating temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM4649I is guaranteed to meet specifications over the –40°C to
125°C internal operating temperature range. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 3: The minimum on-time condition is tested at wafer sort.
Note 4: See output current derating curves for different V
IN
, V
OUT
and T
A
.
Note 5: Guaranteed by design.
Note 6: 100% tested at wafer level.