Datasheet
LTM4644/LTM4644-1
18
Rev. F
For more information www.analog.com
Figure 8. Graphical Representation of JESD 51-12 Thermal Coefficients
4644 F08
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
is used to accurately build the mechanical geometry of
the LTM4644 and the specified PCB with all of the cor-
rect material
coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4644 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power loss
as that which was simulated. An outcome of this process
and due diligence yields the set of derating curves shown
in this data sheet.
The 1V to 5V power loss curves in Figures 9 to 15 can
be used in coordination with the load current derating
curves in Figures 16 to 29 for calculating an approximate
θ
JA
thermal resistance for the LTM4644 with various heat
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are
increased with
a
multiplicative factor according to the junction temperature.
This approximate factor is 1.35 for 120°C. The derating
curves are plotted with the output current starting at 16A
and the ambient temperature at 30°C. These are chosen
to include the lower and higher output voltage ranges
APPLICATIONS INFORMATION
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in a
controlled temperature chamber along with thermal mod
-
eling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
airflow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operat
-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure 16 the load
current is derated to 9.6A at ~90°C with 400LFM of airflow
and no heat sink and the power loss for the 12V to 1.0V
at 9.5A output is about 3.2W. The 3.2W loss is calculated
with 4 times the 0.6W room temperature
loss
from the
12V to 1.0V power loss curve each channel at 2.4A, and
the 1.35 multiplying factor at 120°C junction. If the 90°C
ambient temperature is subtracted from the 120°C junc
-
tion temperature
, then the difference of 30°C divided by
3.2W equals ~9.4°C/W θ
JA
thermal resistance. Table 3
specifies a 10°C/W value which is very close. Tables 3 to
6 provide equivalent thermal resistances for the different
outputs with and without airflow and heat sinking. The
derived thermal resistances in Tables 3 to 6 for the various
conditions can be multiplied by the calculated power loss
as a function of ambient temperature to derive temperature
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