Datasheet

LTM4637
17
4637fc
For more information www.linear.com/LTM4637
applicaTions inForMaTion
A graphical representation of the aforementioned ther-
mal resistances
is given in Figure 7; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op
-
erating conditions
of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally con-
duct exclusively
through the top or exclusively through
bottom of the µModule package—as the standard defines
for θ
JCtop
and θ
JCbottom
, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4637, be aware there are multiple power
devices and components dissipating power, with a con
-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing
modeling
simplicity
—but
also not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reason
-
ably define and correlate the thermal resistance values
supplied
in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4637 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4637 with heat sink and airflow;
(4) having solved for and analyzed these thermal resis
-
tance values and simulated various operating conditions
in
the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operat
-
ing the device at the same power loss as that which was
simulated.
The outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.
The 1V, 2.5V and 5V power loss
curves in Figures 8
to 10
can be used in coordination with the load current derating
curves in Figures 11 to 20 for calculating an approximate
θ
JA
thermal resistance for the LTM4637 with various
heat sinking and airflow conditions. The power loss
curves are taken at room temperature and are increased
with a multiplicative factor according to the junction
temperature, which is 1.4 for 120°C. The derating curves
are plotted with the output current starting at 20A and the
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
4637 F07
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION A
t
CASE (BOTTOM)-TO-BOARD
RESISTANCE