Datasheet

LTM4625
13
Rev D
For more information www.analog.com
APPLICATIONS INFORMATION
The R
FB(SL)
is the feedback resistor and the R
TR(TOP)
/
R
TR(BOT)
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 5.
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR)
is determined by:
MR
SR
=
R
FB(SL)
R
FB(SL)
+ 60.4k
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
For example, V
OUT(MA)
=1.5V, MR = 1.5V/1ms and V
OUT(SL)
= 1.2V, SR = 1.2V/1ms. From the equation, we could solve
that R
TR(TOP)
= 60.4k and R
TR(BOT)
= 40.2k are a good
combination for the ratiometric tracking.
The TRACK/SS pin will have the 2µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on the
TRACK/S
S pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK/SS
pin offset to a negligible value.
Coincident output tracking can be recognized as a special
ratiometric output tracking in which the master’s output
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 6.
From the equation, we could easily find that, in coincident
tracking, the slave regulator’s TRACK/SS pin resistor divider
is always the same as its feedback divider:
R
FB(SL)
R
FB(SL)
+ 60.4k
=
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
For example, R
TR(TOP)
= 60.4k and R
TR(BOT)
= 60.4k is a
good combination for coincident tracking for a V
OUT(MA)
= 1.5V and V
OUT(SL)
= 1.2V application.
Figure 6. Output Coincident Tracking Waveform
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin is pulled
low when the output voltage exceeds a ±10% window
around the regulation point. To prevent unwanted PGOOD
glitches during transients or dynamic V
OUT
changes, the
LTM4625’s PGOOD falling edge includes a blanking delay
of approximately 52 switching cycles.
Stability Compensation
The LTM4625’s internal compensation loop is designed and
optimized for use with low ESR ceramic output capacitors.
Table7 is provided for most application requirements. In
case a bulk output capacitor is required for output ripple
or dynamic transient spike reduction, an additional 10pF
to 15pF feedforward capacitor (C
FF
) is needed between
the V
OUT
and FB pins. The LTpowerCAD design tool is
available for control loop optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4625 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.7V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.2V will turn on the entire chip.
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4625 F06
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