Datasheet

LTC6995-1/LTC6995-2
21
699512fa
For more information www.linear.com/LTC6995-1
Frequency Modulation and Settling Time
The LTC6995 will respond to changes in I
SET
up to a –3dB
bandwidth of 0.4 • f
OUT
.
Following a 2× or 0.5× step change in I
SET
, the output
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
ignores C
LOAD
(valid for C
LOAD
< 1nF) and assumes the
output has 50% duty cycle.
I
S(TYP)
≈ V
+
• f
MASTER
•7.8pF+
V
+
420kΩ
+
V
+
2•R
LOAD
+ 1.8 •I
SET
+ 50µA
Supply Bypassing and PCB Layout Guidelines
The LTC6995 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
applicaTions inForMaTion
–
+
699512 F21
LTC6995-1
RST
GND
SET
OUT
V
+
DIV
C1
0.1µF
R1
R2
R
SET
V
+
R
VCO
V
+
0.1µF
1/2
LTC6078
LTC1659
V
+
V
CC
REF
GND
V
OUT
µP
D
IN
CLK
CS/LD
1MHz • 50kΩ
1024 • N
DIV
• R
VCO
f
OUT
=
D
IN
= 0 TO 4095
• 1 +
–
R
VCO
R
SET
D
IN
4096
(
)
0.1µF
Figure 21. Digitally-Controlled Oscillator
and by following a few rules, the expected performance is
easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 22 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6995. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V
+
and
GND pins using a low inductance path. The connection
from C1 to the V
+
pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.