Datasheet

LTC6995-1/LTC6995-2
12
699512fa
For more information www.linear.com/LTC6995-1
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue moni-
toring V
DIV
for changes. The LTC6995 will respond to
DIVCODE changes in less than one cycle.
t
DIVCODE
< 500 • t
MASTER
< t
OUT
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the mas
-
ter clock period. A digital filter is used to guarantee the
DIVCODE has settled
to a new value before making changes
to the output.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
START
. A supply
voltage of typically 1.4V (1.2V to 1.5V over temperature)
initiates the start-up sequence. The OUT pin is held low
during this time. The typical value for t
START
ranges from
0.5ms to 8ms depending on the master oscillator frequency
(independent of N
DIV
):
t
START(TYP)
= 500 • t
MASTER
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before the output is enabled.
The
start-up time may increase if the supply or DIV pin
voltages
are not stable. For this reason, it is recommended
to
minimize the capacitance on the DIV pin so it will prop-
erly track
V
+
. Less than 100pF will not affect performance.
Start-Up Behavior
When first powered up, the output is held low. If the polarity
is set for non-inversion (POL = 0) and the output is enabled
at the end of the start-up time, OUT will begin oscillating.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain low due to the POL bit = 0. When reset is
released the oscillator starts and the output remains low
for precisely one half cycle of the programmed period.
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6995 does not know the correct
DIVCODE setting when first powered up, so the output
defaults low. At the end of t
START
, the value of DIVCODE is
recognized and OUT goes high (inactive) because POL = 1.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain high due to the POL bit = 1. When reset
is
released
the oscillator starts and the output remains high
for precisely one half cycle of the programmed period.
Figures 7 to 10 detail the possible start-up sequences.
DIV
200mV/DIV
OUT
1V/DIV
10ms/DIV
699512
F05
V
+
= 3.3V
R
SET
= 200k
V
+
1V/DIV
OUT
1V/DIV
250µs/DIV
699512 F06
V
+
= 2.5V
DIVCODE = 15
R
SET
= 50k
500µs
Figure 5. DIVCODE Change from 1 to 0 Figure 6. Typical Start-Up LTC6995-1 with RST = 0V
operaTion