Datasheet

LTC6995-1/LTC6995-2
11
699512fa
For more information www.linear.com/LTC6995-1
t
OUT
1/2 t
OUT
RST
OUT
LTC6995-1
t
RST
t
WIDTH
OUT REMAINS HIGH
WHILE RST IS HIGH
t
OUT
1/2 t
OUT
OUT
LTC6995-2
t
RST
t
WIDTH
OUT REMAINS HIGH
WHILE RST IS LOW
RST
699512 F04
t
OUT
1/2 t
OUT
RST
OUT
LTC6995-1
t
RST
t
WIDTH
OUT REMAINS LOW
WHILE RST IS HIGH
t
OUT
1/2 t
OUT
OUT
LTC6995-2
t
RST
t
WIDTH
OUT REMAINS LOW
WHILE RST IS LOW
RST
699512 F03
operaTion
Reset and Polarity Bit Functions
The Reset input, RST for the LTC6995-1 and RST for the
LTC6995-2, forces the output to a fixed state and resets
the internal clock dividers. The output state when reset is
determined by the polarity bit as selected by through the
DIVCODE setting.
OUTPUT (OSCILLATOR START STATE)
RST/RST POLARITY LTC6995-1 LTC6995-2
0 0 Oscillating (Low) 0 (Reset)
1 0 0 (Reset) Oscillating (Low)
0 1 Oscillating (High) 1 (Reset)
1 1 1 (Reset) Oscillating (High)
With the POL bit programmed to be 0, the output will be
forced low when reset. When reset is released by chang-
ing state
, the oscillator starts. The next rising edge at the
output follows a precise half cycle delay.
With the POL bit programmed to be 1, the output will be
for
ced high when reset. When reset is released by chang
-
ing state, the oscillator starts. The next falling edge at the
output follows a precise half cycle delay.
Figure 3. Reset Timing Diagram (POL Bit = 0)
Figure 4. Reset Timing Diagram (POL Bit = 1)