Datasheet
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
16
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Pulse Width (Duty Cycle) Modulation
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle is
proportional to the voltage applied to the MOD pin, V
MOD
.
Duty Cycle = D =
V
MOD
0.8 • V
SET
−
1
8
The PWM duty cycle accuracy ∆D specifies that the above
equation is valid to within ±4.5% for V
MOD
between 0.2 •
V
SET
and 0.8 • V
SET
(12.5% to 87.5% duty cycle).
Since V
SET
= 1V ±30mV, the duty cycle equation may be
approximated by the following equation.
Duty Cycle = D ≅
V
MOD
−100mV
800mV
The V
MOD
control range is approximately 0.1V to 0.9V.
Driving V
MOD
beyond that range (towards GND or V
+
) will
have no further affect on the duty cycle.
Duty Cycle Limits
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%. At 0% or 100% the output
will stop oscillating and rest at GND or V
+
, respectively.
The LTC6992-2 will never stop oscillating, regardless of
the V
MOD
level. Internal clamping circuits limit its duty
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its V
MOD
control range is 0.14 • V
SET
to 0.86 •
V
SET
(approximately 0.14V to 0.86V).
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
Output Polarity (POL Bit)
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as V
MOD
increases.
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
duty cycle as V
MOD
increases.
operaTion
Figure 3. POL Bit Functionality
6992 F03
OUT
POL = 1
t
OUT
D• t
OUT
OUT
POL = 0
t
OUT
D• t
OUT
D =
V
MOD
0.8 • V
SET
−
1
8
D = 1−
V
MOD
0.8 • V
SET
−
1
8