Datasheet

LTC694-3.3/LTC695-3.3
9
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APPLICATIONS INFORMATION
Microprocessor Reset
The LTC694-3.3/LTC695-3.3 use a bandgap voltage refer-
ence and a precision voltage comparator C1 to monitor the
3.3V supply input on V
CC
(see the Block Diagram). When
V
CC
falls below the reset voltage threshold, the RESET out-
put is forced to active low state. The reset voltage threshold
accounts for a 10% variation on V
CC
, so the RESET output
becomes active low when V
CC
falls below 3.0V (2.9V typi-
cal). On power-up, the RESET signal is held active low for a
minimum of 140ms after reset voltage threshold is reached
to allow the power supply and microprocessor to stabilize.
The reset active time is adjustable on the LTC695-3.3.
On power-down, the RESET signal remains active low
even with V
CC
as low as 1V. This capability helps hold the
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V
CC
pin do
not activate the RESET output. Response time is typically
10ms. To help prevent mistriggering due to transient loads,
the V
CC
pin should be bypassed with a 0.1µF capacitor
with the leads trimmed as short as possible.
The LTC695-3.3 has two additional outputs: RESET and
LOW
_
LINE. RESET is an active high output and is the inverse
of RESET. LOW
_
LINE is the output of the precision voltage
comparator C1. When V
CC
falls below the reset voltage
threshold, LOW
_
LINE goes low. LOW
_
LINE returns high as
soon as V
CC
rises above the reset voltage threshold.
Battery Switchover
The battery switchover circuit compares V
CC
to the V
BATT
input, and connects V
OUT
to whichever is higher. When
V
CC
rises to 70mV above V
BATT
, the battery switchover
comparator, C2, connects V
OUT
to V
CC
through a charge
pumped NMOS power switch, M1. When V
CC
falls to 50mV
above V
BATT
, C2 connects V
OUT
to V
BATT
through a PMOS
switch, M2. C2 has typically 20mV of hysteresis to prevent
spurious switching when V
CC
remains nearly equal to V
BATT
.
The response time of C2 is approximately 20µs.
During normal operation, the LTC694-3.3/LTC695-3.3 use
a charge-pumped NMOS power switch to achieve low
dropout and low supply current. This power switch can
deliver up to 50mA to V
OUT
from V
CC
and has a typical on
resistance of 5. The V
OUT
pin should be bypassed with
a capacitor of 0.1µF or greater to ensure stability. Use of
a larger bypass capacitor is advantageous for supplying
current to heavy transient loads.
When operating currents larger than 50mA are required
from V
OUT
, or a lower dropout (V
CC
– V
OUT
voltage dif-
ferential) is desired, the LTC695-3.3 should be used. This
product provides BATT ON output to drive the base of
an external PNP transistor (Figure 2). If higher currents
are needed with the LTC694-3.3, a high current Schottky
diode can be connected from the V
CC
pin to the V
OUT
pin
to supply the extra current.
V
CC
t
1
t
1
= RESET ACTIVE TIME
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
t
1
V2
V2
V1
V1
694/5-3.3 F01
RESET
LOW LINE
Figure 1. Reset Active Time