Datasheet

LTC694-3.3/LTC695-3.3
5
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V, V
BATT
= 2V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Power-Fail Detector
PFI Input Threshold
l
1.25 1.3 1.35 V
PFI Input Threshold PSRR 0.3 mV/V
PFI Input Current
l
±0.01 ±25 nA
PFO Output Voltage (Note 4) I
SINK
= 800µA
I
SOURCE
= 0.1µA
l
l
2.3
0.3 V
V
PFO Short-Circuit Source Current (Note 4) PFI = HIGH, PFO = 0V
PFI = LOW, PFO = V
OUT
l
13
17
25 µA
µA
PFI Comparator Response Time (Falling) ∆V
IN
= –20mV, V
OD
= 15mV 2 µs
PFI Comparator Response Time (Rising) (Note 4) ∆V
IN
= 20mV, V
OD
= 15mV
with 10k Pull-Up
40
8
µs
µs
Chip Enable Gating
CE IN Threshold V
IL
V
IH
1.9
0.45 V
V
CE IN Pull-Up Current (Note 6) 3µA
CE OUT Output Voltage I
SINK
= 800µA
I
SOURCE
= 400µA
I
SOURCE
= 1µA, V
CC
= 0V
l
l
l
V
OUT
– 0.50
V
OUT
– 0.05
0.3 V
V
V
CE IN Propagation Delay C
L
= 20pF
l
30 50 ns
CE OUT Output Short-Circuit Current Output Source Current
Output Sink Current
15
20
mA
mA
Oscillator
OSC IN Input Current (Note 6) ±2 µA
OSC SEL Input Pull-Up Current (Note 6) 5µA
OSC IN Frequency Range OSC SEL = 0V
OSC SEL = 0V, C
A
= 47pF
l
0
4
125 kHz
kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts, consult the factory.
Note 4: The output pins of BATT ON, LOW
_
LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3µA. However, external pull-
up resistors may be used when higher speed is required.
Note 5: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer. Variation in the timeout
period is caused by phase errors which occur when the oscillator divides
the external clock by 64. The resulting variation in the timeout period is 64
plus one clock of jitter.
Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.