Datasheet

LTC694-3.3/LTC695-3.3
11
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APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10 to 100 series resistor and a 0.1µF capacitor are
recommended to prevent any overshoot beyond V
CC
due
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
BATT
to GND and V
OUT
to V
CC
.
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL STATUS
V
CC
C2 monitors V
CC
for active switchover.
V
OUT
V
OUT
is connected to V
BATT
through an internal PMOS switch.
V
BATT
The supply current is 1µA maximum.
BATT ON Logic high. The open-circuit output voltage is equal to V
OUT
.
PFI Power failure input is ignored.
PFO Logic low.
RESET Logic low.
RESET Logic high. The open-circuit output voltage is equal to V
OUT
.
LOW
_
LINE Logic low.
WDI Watchdog input is ignored.
WDO Logic high. The open-circuit output voltage is equal to V
OUT
.
CE IN Chip
_
Enable input is ignored.
CE OUT Logic high. The open-circuit output voltage is equal to V
OUT
.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by pre-
venting write operations when V
CC
is at invalid level. Two
additional pins, CE IN and CE OUT, control the Chip
_
Enable
or Write inputs of CMOS RAM. When V
CC
is 3.3V, CE OUT
follows CE IN with a typical propagation delay of 30ns.
When V
CC
falls below the reset voltage threshold or V
BATT
,
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the V
BATT
Pin to Ground
While the Battery is Removed, Eliminating Spurious Resets
2.7M
0.1µF
V
BATT
LTC694-3.3
LTC695-3.3
GND
694/5-3.3 F04
10Ω
V
CC
V1
CE IN
V
OUT
= V
BATT
CE OUT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
694/5-3.3 F05
Figure 5. Timing Diagram for CE IN and CE OUT