Datasheet

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LTC694-3.3/LTC695-3.3

69453fb

TYPICAL APPLICATION

FEATURES DESCRIPTION

3.3V Microprocessor

Supervisory Circuits

The LTC

694-3.3/LTC695-3.3 provide complete 3.3V power

supply monitoring and battery control functions. These

include power-on reset, battery back-up, RAM write pro-

tection, power failure warning and watchdog timing. The

devices are pin compatible upgrades of the LTC694/LTC695

that are optimized for 3.3V systems. Operating power

consumption has been reduced to 0.6mW (typical) and

3µW maximum in battery back-up mode. Microprocessor

reset and memory write protection are provided when the

supply falls below 2.9V. The RESET output is guaranteed

to remain logic low with V

as low as 1V.

The LTC694-3.3/LTC695-3.3 power the active RAMs with

a charge pumped NMOS power switch to achieve low

dropout and low supply current. When primary power is

lost, auxiliary power, connected to the battery input pin,

powers the RAMs in standby through an efficient PMOS

switch.

For an early warning of impending power failure, the

LTC694-3.3/LTC695-3.3 provide an internal comparator

with a user-defined threshold. An internal watchdog timer

is also available, which forces the reset pins to active states

when the watchdog input is not toggled prior to a preset

timeout period.

RESET Output Voltage

vs Supply Voltage

APPLICATIONS

Guaranteed Reset Assertion at V

= 1V

Pin Compatible with LTC694/LTC695 for 3.3V Systems

200µA Typical Supply Current

Fast (30ns Typ) Onboard Gating of

RAM Chip Enable Signals

SO-8 and S16 Packages

2.90V Precision Voltage Monitor

Power OK/Reset Time Delay: 200ms or Adjustable

Minimum External Component Count

1µA Maximum Standby Current

Voltage Monitor for Power-Fail or

Low-Battery Warning

Thermal Limiting

Performance Specified Over Temperature

3.3V Low Power Systems

Critical µP Power Monitoring

Intelligent Instruments

Battery-Powered Computers and Controllers

Automotive Systems

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

1µF

≥ 5V

3.3V

100µF

0.1µF

µP

POWER

POWER TO

CMOS RAM

µP

SYSTEM

0.1µF

2.4V

51k

18k

694/5-3.3 TA01

MICROPROCESSOR RESET, BATTERY BACK-UP,

RAM WRITE PROTECTION, POWER WARNING AND

WATCHDOG TIMING ARE ALL IN A SINGLE CHIP

FOR 3.3V MICROPROCESSOR SYSTEM

LTC695-3.3

BATT

PFI

OUT

GND

DECODER OUTPUT

RAM CS

µP RESET

µP NMI

I/O LINE

CE IN

CE OUT

RESET

PFO

WDI

0.1µF

100Ω

GND

OUT

LT1129-3.3

OUT SENSE

SHDN

SUPPLY VOLTAGE (V)

RESET OUTPUT VOLTAGE (V)

694/5-3.3 TA02

Summary of content (20 pages)

PAGE 1
LTC694-3.3/LTC695-3.3 3.3V Microprocessor Supervisory Circuits FEATURES DESCRIPTION n The LTC®694-3.3/LTC695-3.3 provide complete 3.3V power supply monitoring and battery control functions. These include power-on reset, battery back-up, RAM write protection, power failure warning and watchdog timing. The devices are pin compatible upgrades of the LTC694/LTC695 that are optimized for 3.3V systems. Operating power consumption has been reduced to 0.6mW (typical) and 3μW maximum in battery back-up mode.
PAGE 2
LTC694-3.3/LTC695-3.3 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Terminal Voltage VCC.......................................................... –0.3V to 6V VBATT ...................................................... –0.3V to 6V All Other Inputs ..................... –0.3V to (VOUT + 0.3V) Input Current VCC ..................................................................100mA VBATT .................................................................25mA GND ...................................................
PAGE 3
LTC694-3.3/LTC695-3.3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC695CN-3.3#PBF LTC695CN-3.3#TRPBF LTC695CN-3.3 16-Lead PDIP 0°C to 70°C LTC695IN-3.3#PBF LTC695IN-3.3#TRPBF LTC695IN-3.3 16-Lead PDIP –40°C to 85°C LTC695CSW-3.3#PBF LTC695CSW-3.3#TRPBF LTC695CSW-3.3 16-Lead Plastic Wide SO 0°C to 70°C LTC695ISW-3.3#PBF LTC695ISW-3.3#TRPBF LTC695ISW-3.3 16-Lead Plastic Wide SO –40°C to 85°C LTC694CN8-3.3#PBF LTC694CN8-3.
PAGE 4
LTC694-3.3/LTC695-3.3 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VBATT = 2V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 5.50 2.75 V V Battery Back-Up Switching l l 3.0 1.5 l VCC – 0.1 VCC – 0.2 VCC – 0.01 VCC – 0.01 V V IOUT = 50mA l VCC – 0.8 VCC – 0.4 V VOUT in Battery Back-Up Mode IOUT = 250μA, VCC < VBATT l VBATT – 0.1 VBATT – 0.
PAGE 5
LTC694-3.3/LTC695-3.3 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VBATT = 2V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX 1.3 1.35 UNITS Power-Fail Detector l PFI Input Threshold 1.25 PFI Input Threshold PSRR 0.3 V mV/V PFI Input Current l PFO Output Voltage (Note 4) ISINK = 800μA ISOURCE = 0.1μA l l 2.
PAGE 6
LTC694-3.3/LTC695-3.3 TYPICAL PERFORMANCE CHARACTERISTICS Output Voltage vs Load Current 2.40 VCC = 3.3V VBATT = 2.4V TA = 25°C 2.39 OUTPUT VOLTAGE (V) 3.20 SLOPE = 4.6Ω 3.15 3.10 2.38 SLOPE = 90Ω 2.37 2.36 3.05 2.35 10 0 30 40 20 LOAD CURRENT (mA) 100 0 50 300 400 200 LOAD CURRENT (μA) 1.304 1.302 1.300 1.298 500 1.294 –50 –25 Power-Fail Comparator Response Time PFO OUTPUT VOLTAGE (V) 2.5 2.0 VPFI 1.5 1.3V + PFO 30pF – 1.0 0.5 0 3.0 3.5 VCC = 3.3V TA = 25°C 2.5 2.0 1.
PAGE 7
LTC694-3.3/LTC695-3.3 PIN FUNCTIONS BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 25mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. _ CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor’s address line and/or decoder output.
PAGE 8
LTC694-3.3/LTC695-3.3 PIN FUNCTIONS WDI: Watchdog Input. WDI is a three-level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the watchdog timer. The timer resets itself with each transition of the watchdog input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog timeout period, WDO goes low.
PAGE 9
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION Microprocessor Reset Battery Switchover The LTC694-3.3/LTC695-3.3 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the 3.3V supply input on VCC (see the Block Diagram). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 3.0V (2.9V typical).
PAGE 10
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION ANY PNP POWER TRANSISTOR I= VOUT – VBATT R R 5 3 3.3V 0.1μF 1 2.4V 3.3V BATT ON 2 VOUT VCC LTC695-3.3 VCC VOUT 0.1μF 0.1μF LTC694-3.3 LTC695-3.3 0.1μF VBATT GND 4 2.4V VBATT GND 694/5-3.3 F02 694/5-3.3 F03 Figure 2. Using BATT ON to Drive External PNP Transistor Figure 3. Charging External Battery Through VOUT The LTC694-3.3/LTC695-3.3 are protected for safe area operation with short-circuit limit.
PAGE 11
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1μF capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4). 10Ω VBATT 2.7M 0.1μF LTC694-3.3 LTC695-3.3 Table 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. GND 694/5-3.3 F04 Figure 4. 10Ω/0.
PAGE 12
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION VOUT VCC 3.3V 0.1μF VCC + 0.1μF 10μF LTC695-3.3 62512 RAM CE OUT VBATT 2.4V GND CS 30ns PROPAGATION DELAY FROM DECODER CE IN RESET GND Memory protection can also be achieved with the LTC6943.3 by using RESET as shown in Figure 7. RESET TO μP 694/5-3.3 F06 Figure 6. A Typical Nonvolatile CMOS RAM Application VCC 3.3V 0.1μF VOUT VCC + 0.1μF 10μF 62128 RAM CS1 LTC694-3.3 CS RESET GND VBATT 2.4V CS2 GND 694/5-3.3 F07 Figure 7.
PAGE 13
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION Example 1: The circuit in Figure 8 demonstrates the use of the power-fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 5V which is 1.6V greater than the sum of maximum reset voltage threshold and the dropout voltage of the LT1129-3.
PAGE 14
LTC694-3.3/LTC695-3.3 APPLICATIONS INFORMATION VCC = 3.3V WDI t1 = RESET ACTIVE TIME t2 = NORMAL WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER A RESET WDO t2 t3 RESET t1 t1 694/5-3.3 F11 Figure 11. Watchdog Timeout Period and Reset Active Time EXTERNAL OSCILLATOR EXTERNAL CLOCK 3.3V 3 VCC OSC SEL 8 3.3V 3 VCC GND OSC IN 4 7 INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG 3.
PAGE 15
LTC694-3.3/LTC695-3.3 TYPICAL APPLICATION Table 2. LTC695-3.3 Reset Active Time and Watchdog Timeout Selections WATCHDOG TIMEOUT PERIOD RESET ACTIVE TIME OSC SEL OSC IN NORMAL (SHORT PERIOD) IMMEDIATELY AFTER RESET (LONG PERIOD) LTC695-3.3 Low External Clock Input 1024 CLKs 4096 CLKs 2048 CLKs Low External Capacitor* 400ms •C 70pF 1.6s •C 70pF 800ms •C 70pF Floating or High Low 100ms 1.6 sec 200ms Floating or High Floating or High 1.6 sec 1.
PAGE 16
LTC694-3.3/LTC695-3.3 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow 0.300) (Reference LTC DWG # 05-08-1510) .300 – .325 (7.620 – 8.255) .065 (1.651) TYP 8 7 6 5 1 2 3 4 .255 p .015* (6.477 p 0.381) +.035 .325 –.015 8.255 .130 p .005 (3.302 p 0.127) .045 – .065 (1.143 – 1.651) .008 – .015 (0.203 – 0.381) .400* (10.160) MAX .120 (3.048) .020 MIN (0.508) MIN .018 p .003 .100 (2.54) BSC +0.889 –0.381 (0.457 p 0.076) N8 1002 NOTE: 1.
PAGE 17
LTC694-3.3/LTC695-3.3 PACKAGE DESCRIPTION N Package 16-Lead PDIP (Narrow 0.300) (Reference LTC DWG # 05-08-1510) .770* (19.558) MAX 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 .255 ± .015* (6.477 ± 0.381) .130 ± .005 (3.302 ± 0.127) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 +0.889 8.255 –0.381 NOTE: 1. DIMENSIONS ARE ) .045 – .065 (1.143 – 1.651) .020 (0.508) MIN .065 (1.651) TYP .120 (3.048) MIN .100 (2.
PAGE 18
LTC694-3.3/LTC695-3.3 PACKAGE DESCRIPTION SW Package 16-Lead Plastic Small Outline (Wide 0.300) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .398 – .413 (10.109 – 10.490) NOTE 4 16 N 15 14 13 12 11 10 9 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) 3 4 5 6 .093 – .104 (2.362 – 2.
PAGE 19
LTC694-3.3/LTC695-3.3 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 3/10 Removed “UL Recognized” and UL file number from the Features section. 1 69453fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 20
LTC694-3.3/LTC695-3.3 TYPICAL APPLICATION Write Protect for Additional RAMs 3.3V VOUT VCC 0.1μF LTC695-3.3 CE OUT VBATT 2.4V CE IN VCC + 0.1μF LH5168SH RAM A 10μF CS 30ns PROPAGATION DELAY CS A LOW LINE GND VCC 0.1μF CS B LH5116S RAM B CS1 CS2 VCC 0.1μF CS C LH5116S RAM C CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs 694/5-3.3 TA04 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1326 Micropower Precision Triple Supply Monitor 4.725V, 3.118V, 1V Thresholds (0.