Datasheet

LTC6945
9
6945f
V
REF
+
(Pin 26): 3.15V to 3.45V Positive Supply Pin for
Reference Input Circuitry. This pin should be bypassed
directly to the ground plane using a 0.1μF ceramic capaci-
tor as close to the pin as possible.
REF
+
, REF
–
(Pins 27, 28): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider and reference buffer.
They are self-biased and must be AC-coupled with 470pF
capacitors. If used single-ended, bypass REF
–
to GND with
a 470pF capacitor.
GND (Exposed Pad Pin 29): Negative Power Supply
(Ground). The package exposed pad must be soldered
directly to the PCB land. The PCB land pattern should
have multiple thermal vias to the ground plane for both
low ground inductance and also low thermal resistance.
PIN FUNCTIONS
BLOCK DIAGRAM
RF
–
28
2
3
11
GND
10
MUTE
9
RF
+
12
V
RF
+
13
27
REF
–
REFO
≤250MHz
≤100MHz
÷1 TO 1023
÷1 TO 6, 50%
÷32 TO 65535
350MHz
TO 6GHz
MUTE
1
V
REFO
+
REF
+
26
V
REF
+
R_DIV
LOCK
PFD
O_DIV
N_DIV
16
15
CP
V
VCO
+
GND
GND
GND
GND
GND
VCO
+
VCO
–
250μA TO
11.2mA
25
22
21
20
19
18
17
24
V
CP
+
23
GND
6945 BD
14
BB
350MHz TO 6GHz
SERIAL
PORT
STAT
CS
7
SDO
SDI
SCLK
8
V
D
+
6
5
4