Datasheet

LTC6945
17
6945f
OPERATION
Table 9. Serial Port Register Bit Field Summary
Table 8. Serial Port Register Contents
ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT
h00 * * UNLOCK * * LOCK THI TLO R
h01 * * x[5] * * x[2] x[1] x[0] R/W h04
h02 PDALL PDPLL * PDOUT PDREFO * OMUTE POR R/W h0E
h03 * * * * * * RD[9] RD[8] R/W h00
h04 RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] R/W h01
h05 ND[15] ND[14] ND[13] ND[12] ND[11] ND[10] ND[9] ND[8] R/W h00
h06 ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] R/W hFA
h07 * * * * * * * LKEN R/W h01
h08 BST FILT[1] FILT[0] RFO[1] RFO[0] OD[2] OD[1] OD[0] R/W hF9
h09 LKWIN[1] LKWIN[0] LKCT[1] LKCT[0] CP[3] CP[2] CP[1] CP[0] R/W h9B
h0A CPCHI CPCLO CPMID CPINV CPWIDE CPRST CPUP CPDN R/W hE4
h0B REV[2] REV[1] REV[0] PART[4] PART[3] PART[2] PART[1] PART[0] R h40
*unused
BITS DESCRIPTION DEFAULT
BST REF Buffer Boost Current 1
CP[3:0] CP Output Current hB
CPCHI CP Enable Hi Voltage Output Clamp 1
CPCLO CP Enable Low Voltage Output Clamp 1
CPDN CP Pump Down Only 0
CPINV CP Invert Phase 0
CPMID CP Bias to Mid-Rail 1
CPRST CP Three-State 1
CPUP CP Pump Up Only 0
CPWIDE CP Extend Pulse Width 0
FILT[1:0] REF Input Buffer Filter h3
LKCT[1:0] PLL Lock Cycle Count h1
LKEN PLL Lock Indicator Enable 1
LKWIN[1:0] PLL Lock Indicator Window h2
LOCK PLL Lock Indicator Flag
ND[15:0] N Divider Value (ND[15:0] > 31) h00FA
BITS DESCRIPTION DEFAULT
OD[2:0] Output Divider Value (0 < OD[2:0] < 7) h1
OMUTE Mutes RF Output 1
PART[4:0] Part Code h00
PDALL Full Chip Power-Down 0
PDOUT Powers Down O_DIV, RF Output Buffer 0
PDPLL Powers Down REF, REFO, R_DIV, PFD,
CPUMP, N_DIV
0
PDREFO Powers Down REFO 1
POR Force Power-On Reset Register Initialization 0
RD[9:0] R Divider Value (RD[9:0] > 0) h001
REV[2:0] Rev Code h2
RFO[1:0] RF Output Power h3
THI CP Clamp High Flag
TLO CP Clamp Low Flag
UNLOCK PLL Unlock Flag
x[5,2:0] STAT Output OR Mask h04