Datasheet

LTC6945
15
6945f
OPERATION
Figure 10. Serial Port Write Sequence
Figure 11. Serial Port Read Sequence
Figure 12. Serial Port Single Byte Write
Multiple Byte Transfers
More efficient data transfer of multiple bytes is accom-
plished by using the LTC6945’s register address auto-
increment feature as shown in Figure 13. The serial port
master sends the destination register address in the first
byte and its data in the second byte as before, but continues
sending bytes destined for subsequent registers. Byte 1’s
address is Addr0+1, Byte 2’s address is Addr0+2, and so
on. If the resister address pointer attempts to increment
past 11 (h0B), it is automatically reset to 0.
An example of an auto-increment read from the part is
shown in Figure 14. The first byte of the burst sent from
the serial bus master on SDI contains the destination
register address (Addr0) and an LSB of “1” indicating a
read. Once the LTC6945 detects a read burst, it takes SDO
out of the Hi-Z condition and sends data bytes sequentially,
beginning with data from register Addr0. The part ignores
all other data on SDI until the end of the burst.
Multidrop Configuration
Several LTC6945s may share the serial bus. In this multidrop
configuration, SCLK, SDI and SDO are common between
all parts. The serial bus master must use a separate CS
for each LTC6945 and ensure that only one device has
CS asserted at any time. It is recommended to attach a
high value resistor to SDO to ensure the line returns to a
known level during Hi-Z states.
A6 A5 A4 A3 A2
7-BIT REGISTER ADDRESS
Hi-Z
MASTER–CS
MASTER–SCLK
MASTER–SDI
LTC6945–SD0
A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
8 BITS OF DATA
0 = WRITE
6945 F10
16 CLOCKS
A6 A5 A4 A3 A2
7-BIT REGISTER ADDRESS
Hi-Z
Hi-Z
A1 A0 1
D7X D6 D5 D4 D3 D2 D1 D0 DX
8 BITS OF DATA
1 = READ
6945 F11
MASTER–CS
MASTER–SCLK
MASTER–SDI
LTC6945–SDO
16 CLOCKS
Addr0 + Wr
Hi-Z
MASTER–CS
MASTER–SDI
LTC6945–SDO
Byte 0
Addr1 + Wr Byte 1
6945 F12