Datasheet

LTC6915
14
6915fb
operaTion
Figure 4. 2 PGAs in a Daisy Chain
The amplifier’s gain is set as follows:
D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101~
1111
Gain 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096
Input Voltage Range
The input common mode voltage range of the LTC6915
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
V
–
≤ (V
IN
+
– V
IN
–
) + V
REF
≤ V
+
– 1.3
Where V
IN
+
and V
IN
–
are the voltage of the differential
input pins, V
+
and V
–
are the positive and negative sup-
ply voltages respectively and V
REF
is the voltage of REF
pin. In addition, V
IN
+
and V
IN
–
must not exceed the power
supply voltages, i.e.,
V
–
< V
IN
+
< V
+
and V
–
< V
IN
–
< V
+
±5 Volt Operation
When using the LTC6915 with supplies over 5.5V, care must
be taken to limit the maximum difference between any of
the input pins (IN
+
or IN
–
) and the REF pin to 5.5V, i.e.,
|V
IN
+
– V
REF
| < 5.5 and |V
IN
–
– V
REF
| < 5.5
If not, the device will be damaged. For example, if rail-
to-rail input operation is desired when the supplies are at
±5V, the REF pin should be 0, ±0.5V. As a second example,
if the V
+
pin is 10V, and the V
–
and REF pins are at 0, the
inputs should not exceed 5.5V.
SHDN
IN
–
IN
+
V
–
HOLD_THRU
CS(D0)
D
IN
(D1)
CLK(D2)
V
+
OUT
SENSE
REF
NC
P/S
DGND
D
OUT
(D3)
LTC6915
#2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
OUT
D
OUT
V
IN
0.1µFSHDN
IN
–
IN
+
V
–
HOLD_THRU
CS(D0)
D
IN
(D1)
CLK(D2)
V
+
OUT
SENSE
REF
NC
P/S
DGND
D
OUT
(D3)
LTC6915
#1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
OUT
V
IN
0.1µF
0.1µF
0.1µF
0.1µF
µP
–5V –5V
–5V
0.1µF
–5V
6915 F04
CS
D
IN
CLK
CLK
D
IN
CS/LD
D15 D11 D10 D9 D8 D7 D3 D2 D1 D0
GAIN CODE FOR #2
GAIN CODE FOR #1