Datasheet
LTC6915
13
6915fb
operaTion
D
OUT
is always active in serial mode (never tri-stated).
This simplifies the daisy chaining of the multiple devices.
D
OUT
cannot be “wire-or” to other SPI outputs. In addition,
D
OUT
does not return to zero at the end of transmission,
i.e. when CS is pulled high.
A LTC6915 may be daisy-chained with other LTC6915s
or other devices having serial interfaces by connecting
the D
OUT
to the D
IN
of the next chip while CLK and CS
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS signal is pulled
high to update all of them simultaneously. Figure 4
shows an example of two LTC6915s in a daisy chained SPI
configuration.
Figure 1. PGA in the Parallel Control Mode
Figure 2. Bidirectional Nature of D
OUT
/D3 Pin Figure 3. Diagram of Serial Interface (MSB First Out)
4-BIT GAIN
CONTROL CODE
4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
D
OUT
(D3)
CLK
D
IN
CS
6915 F03
V
–
V
+
DGND
D
OUT
(D3)
6915 F02
(INTERNAL
NODE)
SHDN
IN
–
IN
+
V
–
HOLD_THRU
CS(D0)
D
IN
(D1)
CLK(D2)
V
+
OUT
SENSE
REF
NC
P/S
DGND
D
OUT
(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
OUT
V
IN
0.1µF
PARALLEL GAIN CONTROL CODE = 1010
V
OUT
= 2
9
V
IN
= 512V
IN
SHDN
IN
–
IN
+
V
–
HOLD_THRU
CS(D0)
D
IN
(D1)
CLK(D2)
V
+
OUT
SENSE
REF
NC
P/S
DGND
D
OUT
(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
OUT
V
IN
0.1µF
GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR
ON D
OUT
(D3) PROTECT THE DEVICE WHEN V
D3
> V
+
µP
5V 5V
D0
D1
D2
D3
10k
6915 F01