Datasheet

LTC6909
7
6909fa
block DiAgrAM
OUT1
6909 BD
V
+
A
SET
16
MOD
5
OUT2
6
OUT3
7
OUT4
8
OUT5
9
OUT6
10
OUT7
11
OUT8
12
1
OUTPUT
PHASING
DRIVERS
POR
PH0 PH1 PH2 V
+
D
(SSFM = OFF)
3-STATE
INPUT DECODER
WHEN A CLOCK SIGNAL IS PRESENT AT THE
MOD PIN INPUT, THE MODULATION IS DISABLED
PSEUDORANDOM
CODE GENERATOR
–
+
f
MASTER
= 20MHz • 10k • = 20MHz • 10k/R
SET
V
+
– V
SET
MASTER
OSCILLATOR
I
MASTER
I
MASTER
I
REF
MDAC
V
BIAS
R
SET
V
SET
OUT
V
V
+
GND
14
GND
2
+
–
+
–
I
SET
=
R
SET
V
+
– V
SET
3 4 15 13
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
OUTPUT
Hi-Z
UNTIL
STABLE
DIVIDE BY
16/32/64
DETECT
CLOCK INPUT
1 POLE
LPF