Datasheet

LTC6906
5
6906fc
PIN FUNCTIONS
OUT (Pin 1): Oscillator Output. The OUT pin swings from
GND to V
+
with an output resis tance of approximately
150Ω. For micropower operation, the load re sistance must
be kept as high as possible and the load capacitance as
low as possible.
GND (Pin 2): Ground.
DIV (Pin 3): Divider Setting Input. This three-level input
selects one of three internal digital divider settings, de-
termining the value of N in the frequency equation. Tie to
GND for ÷1, leave floating for ÷3 and tie to V
+
for ÷10.
When left floating, the LTC6906 pulls Pin 3 to mid-supply
with a 2.5M resistor. When Pin 3 is floating, care should
be taken to reduce coupling from the OUT pin and its
trace to Pin 3. Coupling can be reduced by increasing the
physical space between traces or by shielding the DIV pin
with grounded metal.
SET (Pin 4): Frequency Setting Resistor Input. Connect
a resistor, R
SET
, from this pin to GND to set the oscillator
frequency. For best perform ance use a precision metal- or
thin-film resistor of 0.5% or better tolerance and 50ppm/°C
or better temperature coefficient. For lower accu racy ap-
plications, an inexpensive 1% thick-film resistor may be
used. Limit the capacitance in parallel with R
SET
to less
than 10pF to reduce jitter and to ensure stability. Capaci-
tance greater than 10pF could cause the LTC6906 internal
feedback circuits to oscillate. The volt age on the SET pin
is approximately 650mV and decreases with temperature
by about –2.2mV/°C.
GRD (Pin 5): Guard Signal. This pin can be used to reduce
PC board leakage across the frequency setting resistor,
R
SET
. The GRD pin is held within a few millivolts of the
SET pin and shunts leakage current away from the SET pin.
To control leakage, connect a bare copper trace (a trace
with no solder mask) to GRD and loop it around the SET
pin and all PC board metal connected to SET.
V
+
(Pin 6): Voltage Supply (2.25V to 3.6V). This supply
is internally decoupled with a 20Ω resistor in series with
an 800pF capacitor. No external decoupling capacitor is
required for OUT pin loads less than 50pF. V
+
should be
kept reasonably free of noise and ripple.
BLOCK DIAGRAM
+
4
6
1
OP AMP
f
OSC
150Ω DRIVER
f
OSC
I
FB
I
FB
OUT
6906 BD
3
DIV
PROGRAMMABLE
DIVIDER (n)
(1, 3, 10)
THREE-LEVEL
INPUT
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
(MASTER OSCILLATOR)
f
OSC
.)[tLĀ3
SET
SET
V
+
2
GND
20
800pF
V
SET
V
GRD
650mV
I
SET
= I
FB
FREQUENCY-TO-CURRENT
CONVERTERS
DECOUPLING
NETWORK
BUFFER
GRD
R
SET
5M
5M
DIVIDER
SELECT
V
+
V
SET
V
SET
V
SET
5