Datasheet
LTC6902
8
6902f
THEORY OF OPERATIO
U
As shown in the Block Diagram, the LTC6902’s master
oscillator is controlled by the ratio of the voltage between
the V
+
and SET pins (V
+
– V
SET
) and the current entering
the master oscillator, I
MASTER
. When the spread spectrum
frequency modulation (SSFM) is disabled, I
MASTER
is
strictly determined by the V
+
– V
SET
voltage and the I
SET
current. When SSFM is enabled, the current I
MOD
(modu-
lation current) is subtracted from the I
SET
current to
determine the I
MASTER
current value. Here the I
MASTER
current is maximally at I
SET
but more often than not it is
less than I
SET
by a value determined by the I
MOD
value. In
this way the frequency of the master oscillator is modu-
lated to produce a frequency that is always less than or
equal to the frequency set by the I
SET
current.
The voltage on the SET pin is forced to approximately 1.1V
below V
+
by the PMOS transistor and its gate bias voltage.
This voltage is accurate to ±8% at a particular input
current and supply voltage (see Figure 2). The R
SET
resistor, connected between the V
+
and SET pins, locks
together the (V
+
– V
SET
) voltage and the current I
SET
. This
allows the parts to attain excellent frequency accuracy
regardless of the precision of the SET pin voltage. The
LTC6902 is optimized for use with R
SET
resistors between
10k and 2M. This corresponds to master oscillator fre-
quencies between 100kHz and 20MHz. Additionally, the
MOD pin’s voltage tracks the SET pin’s voltage. The R
MOD
resistor connected between the V
+
and MOD pins similarly
locks together the MOD pin voltage variation and the I
MOD
current to once more yield excellent accuracy.
The master oscillator’s output is connected to the pro-
grammable divider. The output of the programmable
divider is then connected to the multiphase circuit with its
four outputs directly connected to output drivers. The final
output frequency is determined by the R
SET
resistor value,
the programmable divider setting and the multiphase
mode selected. The formula for setting the output fre-
quency, f
OUT
, is below:
f
MHz
NM
k
R
OUT
SET
=•
Ω
10 20
•
where:
N Open
V
M H Open
HV
=
=
=
=
=
=
=
=
+
+
100
10
1
4
3
1
DIV Pin V
DIV Pin
DIV Pin 0
(4-Phase Output) PHPin V
(3-Phase Output) P Pin
(2-Phase Output) P Pin 0
When the spread spectrum frequency modulation (SSFM)
is disabled, the frequency f
OUT
is the final output fre-
quency. When SSFM is enabled, f
OUT
is the maximum
output frequency with the R
MOD
resistor value determin-
ing the minimum output frequency.
The programmable divider divides the master oscillator
signal by 1, 10 or 100. The divide-by value is determined
by the state of the DIV input (Pin 2). Tie DIV to GND or drive
it below 0.5V to select ÷1. This is the highest frequency
range, with the master output frequency passed directly to
the multiphase circuit. The DIV pin may be floated or
driven to midsupply to select ÷10, the intermediate fre-
quency range. The lowest frequency range, ÷100, is se-
lected by tying DIV to V
+
or driving it to within 0.4V of V
+
.
Figure 3 shows the relationship between R
SET
, divider
setting and output frequency, including the overlapping
frequency ranges near 100kHz and 1MHz.
The multiphase circuit generates outputs that are either
2-, 3- or 4-phase waveforms. To generate the 3- and
4-phase output signals, the output from the programmable
Figure 2. V
+
– V
SET
Variation with I
RES
I
RES
(µA)
10.1
0.8
V
RES
= V
+
– V
SET
1.2
1.3
1.4
10 100 1000
69012 F02
1.1
1.0
0.9
V
+
= 5V
V
+
= 3V
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