Datasheet

LTC6802-2
9
68022fa
pin FuncTions
pin becomes high impedance. Either a “1” or a “0” is read
back, depending on the voltage present at Pin 35. The
GPIOs make it possible to turn on/off circuitry around
the LTC6802-2, or read logic values from a circuit around
the LTC6802-2.
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See Monitor Mode in the Applications
Information section.
A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs.
These pins are tied to V
REG
or V
–
. The state of the address
pins (V
REG
= 1, V
–
= 0) determines the LTC6802-2 address.
See LTC6802-2 Address Commands in the Serial Port
subsection of the Applications Information section.
SCKI (Pin 41): Serial Clock Input. The SCKI pin inter-
faces to any logic gate (TTL levels). See Serial Port in the
Applications Information section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels). See Serial Port in the Applica-
tions Information section.
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
open drain output and requires an external resistor pull-up.
See Serial Port in the Applications Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels). See Serial
Port in the Applications Information section.
block DiagraM
RESULTS
REGISTER
AND
COMMUNICATIONS
REFERENCE
∆∑ A/D CONVERTER
CONTROL
WATCHDOG
TIMER
REGULATOR
DIE
TEMP
V
TEMP2
V
REF
V
TEMP1
EXTERNAL
TEMP
68022 BD
1
V
+
2
C12
3
S12
4
C11
22
C2
23
S2
24
C1
25
S1
26
V
–
27
NC
40
A3
34
WDTB
31
V
REG
39
A2
38
A1
37
A0
44
CSBI
43
SDO
42
SDI
41
SCKI
36
GPIO2
35
GPIO1
33
MMB
32
TOS
28 29 30
10Ω
10k
10k
10k
10k
21
S3
MUX
12