Datasheet

LTC6802-2
8
68022fa
pin FuncTions
V
+
(Pin 1): Tie Pin 1 to the most positive potential in
the battery stack. V
+
must be approximately the same
potential as C12.
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1
(Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1
through C12 are the inputs for monitoring battery cell
voltages. Up to 12 cells can be monitored. The lowest
potential is tied to the V
pin. The next lowest potential
is tied to C1 and so forth. See the figures in the Applica-
tions Information section for more details on connecting
batteries to the LTC6802-2.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1
(Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes over charged, an S output can be used to
discharge the cell. Each S output is an internal N-channel
MOSFET for discharging. See the Block Diagram. The NMOS
has a maximum on-resistance of 20Ω. An external resistor
should be connected in series with the NMOS to dissipate
heat outside of the LTC6802-2 package. When using the
internal MOSFETs to discharge cells, the die temperature
should be monitored. See Power Dissipation and Thermal
Shutdown in the Applications Information section.
The S pins also feature an internal 10k pull-up resistor. This
allows the S pins to be used to drive the gates of external
P-channel MOSFETs for higher discharge capability.
V
(Pin 26): Connect V
to the most negative potential in
the series of cells.
NC (Pin 27): Pin 27 is internally connected to V
through
10Ω. Pin 27 can be left unconnected or connect Pin 27
to Pin 26 on the PCB.
V
TEMP1
, V
TEMP2
(Pins 28, 29): Temperature Sensor Inputs.
The ADC will measure the voltage on V
TEMPx
with respect
to V
and store the result in the TMP register. The ADC
measurements are relative to the V
REF
pin voltage. Therefore
a simple thermistor and resistor combination connected
to the V
REF
pin can be used to monitor temperature. The
V
TEMP
inputs can also be general purpose ADC inputs.
V
REF
(Pin 30): 3.075V Voltage Reference Output. This pin
should be bypassed with a 1µF capacitor. The V
REF
pin can
drive a 100k resistive load connected to V
. Larger loads
should be buffered with an LT6003 op amp, or similar
device.
V
REG
(Pin 31): Linear Voltage Regulator Output. This pin
should be bypassed with a 1µF capacitor. The V
REG
is
capable of sourcing up to 4mA to an external load. The
V
REG
pin does not sink current.
TOS (Pin 32): Top of Stack Input. The TOS pin can be tied
to V
REG
or V
for the LTC6802-2. The state of the TOS pin
alters the operation of the SDO pin in the toggle polling
mode. See the Serial Port description.
MMB (Pin 33): Monitor Mode Input (Active Low). When
MMB is low (same potential as V
), the LTC6802-2
goes into monitor mode. See Modes of Operation in the
Applications Information section.
WDTB (Pin 34): Watchdog Timer Output (Active Low). If
there is no activity on the SCKI pin for 2.5 seconds, the
WDTB output is asserted. The WDTB pin is an open-drain
NMOS output. When asserted it pulls the output down
to V
and resets the configuration register to its default
state. See Watchdog Timer Circuit in the Applications
Information section.
GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/Out-
put. The operation of these pins depends on the state of
the MMB pin.
When MMB is high, the pins behave as traditional GPIOs.
By writing a “0” to a GPIO configuration register bit, the
open drain output is activated and the pin is pulled to V
.
By writing a logic “1” to the configuration register bit, the
corresponding GPIO pin is high impedance. An external
resistor is needed to pull the pin up to V
REG
.
By reading the configuration register locations GPIO1
and GPIO2, the state of the pins can be determined. For
example, if a “0” is written to register bit GPIO1, a “0”
is always read back because the output NMOSFET pulls
Pin
35 to V
. If a “1” is written to register bit GPIO1, the