Datasheet

LTC6802-2
29
68022fa
applicaTions inForMaTion
Figure 16. Providing an Isolated High-Speed Data Interface
LTC6802-2
68022 F16
CSBI
V
−
V
REG
SDO
SDI
SCKI
LTC1693-2
ACSL-6410
IN1
GND1
IN2
GND2
V
CC1
OUT1
V
CC2
OUT2
3.57k 3.57k 3.57k
330Ω
+5V_HOST
CSBI
SDI
SCKI
SDO
GND_HOST
4.99k
33nF
1
3
6
4
1µF
BAT54S
ISOLATED V
LOGIC
PE68386
BAT54S
••
470pF
100nF
1µF
20k
10k
330Ω
100k
TP0610K
330Ω
TP0610K
100k
TP0610K
100k
249Ω
PROVIDING HIGH SPEED OPTO-ISOLATION
OF THE SPI DATA PORT
Isolation techniques that are capable of supporting the
1Mbps data rate of the LTC6802-2 require more power
on the isolated (battery) side than can be furnished by
the V
REG
output of the LTC6802-2. To keep battery drain
minimal, this means that a DC/DC function must be imple-
mented along with a suitable data isolation circuit, such as
shown in Figure 16. Here an optimal Avago 4-channel (3/1
bidirectional) opto-coupler is used, with a simple isolated
supply generated by an LTC1693-2 configured as a 200kHz
oscillator. The DC/DC function provides an unregulated
logic voltage (~4V) to the opto-coupler isolated side,
from energy provided by host-furnished 5V. This circuit
provides totally galvanic isolation between the batteries
and the host processor, with an insulation rating of 560V
continuous, 2500V transient. The Figure 16 functionality
is included in the LTC6802-2 demo board.
PCB LAYOUT CONSIDERATIONS
The V
REG
and V
REF
pins should be bypassed with a 1µF
capacitor for best performance.
The LTC6802-2 is capable of operation with as much as
60V between V
+
and V
–
. Care should be taken on the PCB
layout to maintain physical separation of traces at different
potentials. The pinout of the LTC6802-2 was chosen to
facilitate this physical separation. Figure 17 shows the DC
voltage on each pin with respect to V
–
when twelve 3.6V
battery cells are connected to the LTC6802-2. There is no
more then 5.5V between any two adjacent pins. The pack-
age body is used to separate the highest voltage (43.5V)
from the lowest voltage (0V).