Datasheet

LTC6802-2
26
68022fa
applicaTions inForMaTion
Internal Protection Diodes
Each pin of the LTC6802-2 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 9.
The diodes shown are conventional silicon diodes with a
forward breakdown voltage of 0.5V. The unlabeled Zener
diode structures have a reverse-breakdown characteristic
which initially breaks down at 12V then snaps back to a 7V
clamping potential. The Zener diodes labeled Z
CLAMP
are
higher voltage devices with an initial reverse breakdown
of 30V snapping back to 25V. The forward voltage drop
of all Zeners is 0.5V. Refer to this diagram in the event of
unpredictable voltage clamping or current flow. Limiting
the current flow at any pin to ±10mA will prevent damage
to the IC.
Cell-Voltage Filtering
The LTC6802-2 employs a sampling system to perform
its analog-to-digital conversions and provides a conver-
sion result that is essentially an average over the 0.5ms
conversion window, provided there isn’t noise aliasing with
respect to the delta-sigma modulator rate of 512kHz. This
indicates that a lowpass filter with useful attenuation at
500kHz may be beneficial. Since the delta-sigma integra-
tion bandwidth is about 1kHz, the filter corner need not
be lower than this to assure accurate conversions.
Series resistors of 100Ω may be inserted in the input
paths without introducing meaningful measurement
error, provided only external discharge switch FETs are
being used. Shunt capacitors may be added from the cell
inputs to V
–
, creating RC filtering as shown in Figure 10.
Note that this filtering is not compatible with use of the
internal discharge switches to carry current since this
would induce settling errors at the time of conversion as
any activated switches temporarily open to provide Kelvin
mode cell sensing. As a discharge switch opens, cell wiring
resistance will also form a small voltage step (recovery
of the small IR drop), so keeping the frequency cutoff of
the filter relatively high will allow adequate settling prior
to the actual conversion. A guard time of about 60µs is
provided in the ADC timing, so a 16kHz LP is optimal and
offers about 30dB of noise rejection.
68022 F09
LTC6802-2
S1
V
–
WDTB
CSBI
V
MODE
SDO
SDI
SCKI
GPIO2
GPIO1
MMB
TOS
S2
C1
S3
C2
S4
C3
S5
C4
S6
C5
C6
S7
S8
C7
S9
C8
S10
C9
S11
C10
S12
C11
A3
A2
A1
A0
C12
V
+
Z
CLAMP
Z
CLAMP
Z
CLAMP
Figure 9. Internal Protection Diodes
Figure 10. Adding RC Filtering to the Cell Inputs
(One Cell Connection Shown)
Cn
Sn
Cn – 1
100Ω
100Ω
100nF
6.2V
100nF
68021 F10
+